公开(公告)号：US20170024145A1

公开(公告)日：2017-01-26

申请号：US14807754

申请日：2015-07-23

Applicant: QUALCOMM INCORPORATED

Inventor： TAREK ZGHAL ,  Alain Dominique Artieri ,  Jason Edward Podaima ,  Meghal Varia ,  Serag GadelRab

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/654

Abstract: Systems, methods, and computer program products are disclosed for reducing latency in a system that includes one or more processing devices, a system memory, and a cache memory. A pre-fetch command that identifies requested data is received from a requestor device. The requested data is pre-fetched from the system memory into the cache memory in response to the pre-fetch command. The data pre-fetch may be preceded by a pre-fetch of an address translation. A data access request corresponding to the pre-fetch command is then received, and in response to the data access request the data is provided from the cache memory to the requestor device.

Abstract translation: 公开了系统，方法和计算机程序产品，用于减少包括一个或多个处理设备，系统存储器和高速缓冲存储器的系统中的延迟。 从请求器设备接收到识别所请求数据的预取命令。 响应于预取命令，将所请求的数据从系统存储器预取入高速缓冲存储器。 之前的数据预取可以预先获取地址转换。 然后接收与预取命令相对应的数据访问请求，并且响应于数据访问请求，将数据从高速缓冲存储器提供给请求器设备。

公开(公告)号：US20150161057A1

公开(公告)日：2015-06-11

申请号：US14147555

申请日：2014-01-05

Applicant: Qualcomm Incorporated

Inventor： THOMAS M. ZENG ,  AZZEDINE TOUZNI ,  STEPHEN A. MOLLOY ,  SATYAKI MUKHERJEE ,  ABHIRAMI SENTHILKUMARAN ,  OLAV HAUGAN ,  TZUNG REN TZENG ,  TAREK ZGHAL ,  JEAN-LOUIS O. TARDIEUX ,  AJAY UPADHYAYA ,  ZHURANG ZHAO ,  PAWAN CHHABRA ,  SUBRAHMANYAM MOOLA ,  PAVAN KUMAR ,  JAYDEEP R. CHOKSHI ,  VICTOR K. WONG ,  VIPUL C. GANDHI

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F11/2221 ,  G11C29/18

Abstract: Systems and methods are disclosed for providing memory address translation for a memory management system. One embodiment of such a system comprises a memory device and an application processor in communication via a system interconnect. The application processor comprises test code for testing one or more of a plurality of hardware devices. Each of the hardware devices has a corresponding system memory management unit (SMMU) for processing memory requests associated with the hardware device to the memory device. The system further comprises a client-side address translation system in communication with the system interconnect and the plurality of SMMUs. The client-side address translation system is configured to selectively route stimulus traffic associated with the test code to a client port on one or more of the plurality of SMMUs for testing the corresponding hardware devices.

Abstract translation: 公开了用于为存储器管理系统提供存储器地址转换的系统和方法。 这种系统的一个实施例包括存储器设备和经由系统互连进行通信的应用处理器。 应用处理器包括用于测试多个硬件设备中的一个或多个的测试代码。 每个硬件设备具有相应的系统存储器管理单元（SMMU），用于处理与硬件设备相关联的存储器请求到存储器设备。 该系统还包括与系统互连和多个SMMU通信的客户端地址转换系统。 客户端地址转换系统被配置为选择性地将与测试代码相关联的刺激流量路由到多个SMMU中的一个或多个SMMU上的客户端口，以测试对应的硬件设备。