公开(公告)号：US20190306005A1

公开(公告)日：2019-10-03

申请号：US15939031

申请日：2018-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： KUNAL DESAI ,  SATYAKI MUKHERJEE ,  SIDDHARTH KAMDAR ,  ABHINAV MITTAL ,  VINAYAK SHRIVASTAVA

IPC: H04L29/08 ,  G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.

公开(公告)号：US20150268706A1

公开(公告)日：2015-09-24

申请号：US14304894

申请日：2014-06-14

Applicant: QUALCOMM INCORPORATED

Inventor： TERO KUKOLA ,  CARL VICTOR STREETER ,  THOMAS ZENG ,  AJAYKUMAR SHANKARGOUDA PATIL ,  CHRISTOPHER ALAN PAGNOTTA ,  VINAY JAIN ,  SATYAKI MUKHERJEE ,  AZZEDINE TOUZNI

IPC: G06F1/26 ,  G06F21/64

CPC classification number: G06F21/64 ,  G06F21/81

Abstract: Various embodiments of methods and systems for hardware-based memory power management (“HMPM”) in a portable computing device (“PCD”) running secure and non-secure execution environments are disclosed. Hardware-based state machines are uniquely associated with, and under the control of, the non-secure execution environment, the secure execution environment and a virtual manager, respectively. The states of the state machines constitute votes by each of the execution environments and the virtual manager to control the power supply state to the memory component, such as a cache memory. The votes are monitored by a digital circuit that, based on a combination logic of the votes, generates an output signal to trigger a power management component to maintain, supply or remove power on a rail associated with the memory component. In this way, the power supply state to the memory component cannot be unilaterally changed by an application running in the non-secure execution environment.

Abstract translation: 公开了在运行安全和非安全执行环境的便携式计算设备（“PCD”）中用于基于硬件的存储器功率管理（“HMPM”）的方法和系统的各种实施例。 基于硬件的状态机分别与非安全执行环境，安全执行环境和虚拟管理器独立地相关联并在其控制下。 状态机的状态由每个执行环境和虚拟管理器构成投票，以控制诸如高速缓冲存储器的存储器组件的电源状态。 投票由数字电路监控，该数字电路基于投票的组合逻辑产生输出信号以触发电力管理组件以维持，提供或移除与存储器组件相关联的轨道上的电力。 以这种方式，通过在非安全执行环境中运行的应用程序不能单方面地改变对存储器组件的供电状态。

公开(公告)号：US20150161057A1

公开(公告)日：2015-06-11

申请号：US14147555

申请日：2014-01-05

Applicant: Qualcomm Incorporated

Inventor： THOMAS M. ZENG ,  AZZEDINE TOUZNI ,  STEPHEN A. MOLLOY ,  SATYAKI MUKHERJEE ,  ABHIRAMI SENTHILKUMARAN ,  OLAV HAUGAN ,  TZUNG REN TZENG ,  TAREK ZGHAL ,  JEAN-LOUIS O. TARDIEUX ,  AJAY UPADHYAYA ,  ZHURANG ZHAO ,  PAWAN CHHABRA ,  SUBRAHMANYAM MOOLA ,  PAVAN KUMAR ,  JAYDEEP R. CHOKSHI ,  VICTOR K. WONG ,  VIPUL C. GANDHI

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F11/2221 ,  G11C29/18

Abstract: Systems and methods are disclosed for providing memory address translation for a memory management system. One embodiment of such a system comprises a memory device and an application processor in communication via a system interconnect. The application processor comprises test code for testing one or more of a plurality of hardware devices. Each of the hardware devices has a corresponding system memory management unit (SMMU) for processing memory requests associated with the hardware device to the memory device. The system further comprises a client-side address translation system in communication with the system interconnect and the plurality of SMMUs. The client-side address translation system is configured to selectively route stimulus traffic associated with the test code to a client port on one or more of the plurality of SMMUs for testing the corresponding hardware devices.

Abstract translation: 公开了用于为存储器管理系统提供存储器地址转换的系统和方法。 这种系统的一个实施例包括存储器设备和经由系统互连进行通信的应用处理器。 应用处理器包括用于测试多个硬件设备中的一个或多个的测试代码。 每个硬件设备具有相应的系统存储器管理单元（SMMU），用于处理与硬件设备相关联的存储器请求到存储器设备。 该系统还包括与系统互连和多个SMMU通信的客户端地址转换系统。 客户端地址转换系统被配置为选择性地将与测试代码相关联的刺激流量路由到多个SMMU中的一个或多个SMMU上的客户端口，以测试对应的硬件设备。