公开(公告)号：US20180336141A1

公开(公告)日：2018-11-22

申请号：US15596972

申请日：2017-05-16

Applicant: QUALCOMM INCORPORATED

Inventor： KUNAL DESAI ,  FELIX VARGHESE ,  VASANTHA KUMAR BANDUR PUTTAPPA

IPC: G06F12/1045 ,  G06F12/1009 ,  G06F12/0862

Abstract: Systems, methods, and computer programs are disclosed for reducing worst-case memory latency in a system comprising a system memory and a cache memory. One embodiment is a method comprising receiving a translation request from a memory client for a translation of a virtual address to a physical address. If the translation is not available at a translation buffer unit and a translation control unit in a system memory management unit, the translation control unit initiates a page table walk. During the page table walk, the method determines a page table entry for an intermediate physical address in the system memory. In response to determining the page table entry for the intermediate physical address, the method preloads data at the intermediate physical address to the system cache before the page table walk for a final physical address corresponding to the intermediate physical address is completed.

公开(公告)号：US20190306005A1

公开(公告)日：2019-10-03

申请号：US15939031

申请日：2018-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： KUNAL DESAI ,  SATYAKI MUKHERJEE ,  SIDDHARTH KAMDAR ,  ABHINAV MITTAL ,  VINAYAK SHRIVASTAVA

IPC: H04L29/08 ,  G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.