公开(公告)号：US20180336141A1

公开(公告)日：2018-11-22

申请号：US15596972

申请日：2017-05-16

Applicant: QUALCOMM INCORPORATED

Inventor： KUNAL DESAI ,  FELIX VARGHESE ,  VASANTHA KUMAR BANDUR PUTTAPPA

IPC: G06F12/1045 ,  G06F12/1009 ,  G06F12/0862

Abstract: Systems, methods, and computer programs are disclosed for reducing worst-case memory latency in a system comprising a system memory and a cache memory. One embodiment is a method comprising receiving a translation request from a memory client for a translation of a virtual address to a physical address. If the translation is not available at a translation buffer unit and a translation control unit in a system memory management unit, the translation control unit initiates a page table walk. During the page table walk, the method determines a page table entry for an intermediate physical address in the system memory. In response to determining the page table entry for the intermediate physical address, the method preloads data at the intermediate physical address to the system cache before the page table walk for a final physical address corresponding to the intermediate physical address is completed.

公开(公告)号：US20190205264A1

公开(公告)日：2019-07-04

申请号：US15857062

申请日：2017-12-28

Applicant: QUALCOMM INCORPORATED

Inventor： FELIX VARGHESE ,  ZHENBIAO MA ,  MARTIN JACOB ,  KUMAR SAKET ,  VASANTHA KUMAR BANDUR PUTTAPPA ,  SUJEET KUMAR

IPC: G06F12/1081 ,  G06F12/1045 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/0895 ,  G06F12/0864

CPC classification number: G06F12/1081 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1024 ,  G06F2212/171 ,  G06F2212/304 ,  G06F2212/6082 ,  G06F2212/65 ,  G06F2212/68

Abstract: A MMU may read page descriptors (using virtual addresses as an index) in a burst mode from page tables in a system memory. The page descriptors may include intermediate physical addresses (“IPAs”, in stage 1) and corresponding physical addresses (“PAs”, in stage 2). The virtual address in conjunction with page table base address register is used to index page descriptors into main memory. The MMU may identify a first group of contiguous IPAs beginning at a base IPA and a second group of contiguous IPAs beginning at an offset from the base IPA. The first and second groups may be separated by at least one IPA not contiguous with either the first or second group. The MMU may read a first PA from the page tables that corresponds to the base IPA. The MMU may store an entry in a buffer that includes the PA and a first linearity tag.