公开(公告)号：US20180373314A1

公开(公告)日：2018-12-27

申请号：US15634956

申请日：2017-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD STEWART ,  DEXTER CHUN

IPC: G06F1/32 ,  G06F13/16 ,  G06F13/40

Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.

公开(公告)号：US20180335828A1

公开(公告)日：2018-11-22

申请号：US15600318

申请日：2017-05-19

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER CHUN ,  RICHARD STEWART

IPC: G06F1/32

CPC classification number: G06F13/1689 ,  G06F1/3234 ,  G06F1/3253

Abstract: Systems and methods are disclosed for reducing double data rate (DDR) memory power consumption via device-specific customization of DDR interface parameters. One embodiment comprises a method for minimizing double data rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface electrically coupling a DDR memory to a memory controller residing on a system on chip (SoC). The memory controller executes a memory test via the DDR interface at the selected operating point. During the execution of the memory test at the selected operating point, the method determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.

公开(公告)号：US20170162235A1

公开(公告)日：2017-06-08

申请号：US14957045

申请日：2015-12-02

Applicant: QUALCOMM INCORPORATED

Inventor： SUBRATO DE ,  RICHARD STEWART ,  DEXTER TAMIO CHUN

IPC: G11C7/10 ,  G06F12/06 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1027 ,  G06F13/1657 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power/performance optimization. One such method comprises configuring an interleaved zone for relatively higher performance tasks, a linear address zone for relatively lower power tasks, and a mixed interleaved-linear zone for tasks with intermediate performance requirements. A boundary is defined among the different zones using a sliding threshold address. The zones may be dynamically adjusted, and/or new zones dynamically created, by changing the sliding address in real-time based on system goals and application performance preferences. A request for high performance memory is allocated to a zone with lower power that minimally supports the required performance, or may be allocated to a low power memory zone with lower than required performance if the system parameters indicate a need for aggressive power conservation. Pages may be migrated between zones in order to free a memory device for powering down.

公开(公告)号：US20170139469A1

公开(公告)日：2017-05-18

申请号：US14940065

申请日：2015-11-12

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD STEWART ,  Dexter Tamio Chun ,  Alain Artieri

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3287 ,  Y02D10/172 ,  Y02D50/20

Abstract: Components of a portable computing device produce power supply voltage requests indicating requested power levels. In response to the power supply voltage requests, power multiplexers associated with the components select and couple corresponding voltage rails associated with two or more fixed-voltage power supplies to the requesting components. Power supplies may be activated and deactivated on an as-requested basis.