公开(公告)号：US20180018292A1

公开(公告)日：2018-01-18

申请号：US15209416

申请日：2016-07-13

Applicant: QUALCOMM INCORPORATED

Inventor： KIRAN KUMAR MALIPEDDI ,  YOSSI AMON ,  GRAHAM ROFF ,  CHRISTOPHER KONG YEE CHUN ,  RAJESH CHAVA

IPC: G06F13/24 ,  G06F1/32 ,  G06F1/24

CPC classification number: G06F13/24 ,  G06F1/24 ,  G06F1/3206 ,  G06F13/42

Abstract: Systems and methods are disclosed for resolving bus hang in a computing device. An exemplary system comprises a bus operating in accordance with an interface clock, and a controller in communication with the bus. The controller comprises a finite state machine, where the finite state machine is configured to receive a clock signal from the interface clock and a command signal originating external to the controller. The controller also comprising hang detection logic configured to receive one or more signals that the finite state machine is active, monitor the interface clock, and generate an event notification in response to the interface clock turning off while the finite state machine is active. The controller further comprises a trap handler in communication with the hang detection logic, the trap handler configured to send an interrupt in response to the event notification.

公开(公告)号：US20170346656A1

公开(公告)日：2017-11-30

申请号：US15168066

申请日：2016-05-29

Applicant: QUALCOMM INCORPORATED

Inventor： AJAY NAWANDHAR ,  PAVAN KUMAR ,  KIRAN KUMAR MALIPEDDI ,  CHANDRASEKHAR REDDY RAMREDDY GARI

IPC: H04L12/40 ,  H04L7/04

CPC classification number: G06F13/40 ,  G06F1/3206 ,  G06F1/3275 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for data generator driven bus clock voting are disclosed. An exemplary embodiment defines a first timing domain within a system on a chip to comprise a data generating component and a bus that includes a memory management unit. The bus serves to communicatively couple the data generating component to a memory component, such as a DDR. A second timing domain within the system on a chip comprises the memory component. With such a configuration, the embodiment may leverage the clock speed of the data generating component to set a clock speed for components in the first timing domain and, in doing so, the clock speed of the memory management unit is dictated by the first timing domain.