公开(公告)号：US20130229212A1

公开(公告)日：2013-09-05

申请号：US13866871

申请日：2013-04-19

Applicant: QUALCOMM INCORPORATED

Inventor： Jeremy D. Dunworth ,  Gary J. Ballantyne ,  Bhushan S. Asuri ,  Jifeng Geng ,  Gurkanwal S. Sahota

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/093

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract translation: 在锁相环（PLL）处执行数据信号的调制的方法包括至少部分地基于数据信号在PLL的高频端口生成数字环路信号。 该方法还包括区分数字环路信号以产生数字输入信号并将数字输入信号转换为模拟电流信号。 基于模拟电流信号产生第一反馈信号。 该方法还包括在PLL的较低频率端口处产生基于第一反馈信号的第二反馈信号，并且还基于该数据信号。 根据另外的实施例，公开了装置和计算机可读介质。

公开(公告)号：US08818311B2

公开(公告)日：2014-08-26

申请号：US13725151

申请日：2012-12-21

Applicant: QUALCOMM Incorporated

Inventor： Charles J. Persico ,  Jeremy D. Dunworth

IPC: H04B17/00

CPC classification number: H04B1/16 ,  H03D3/004 ,  H03D7/165 ,  H03G3/3052 ,  H03G3/3078 ,  H03J7/04 ,  H04W52/029 ,  Y02D70/142 ,  Y02D70/23 ,  Y02D70/40

Abstract: A method of harmonic selection for mixing with a received signal includes receiving a radio frequency (RF) signal and determining a variable gain setting from among a plurality of gain settings or from a range of gain settings. The variable gain setting is based on the RF signal. The method further includes selecting a harmonic to provide to an input of a mixer to generate an output signal. A baseband signal or an intermediate frequency signal is generated from the output signal. The harmonic is selected based on the variable gain setting. An apparatus includes a harmonic selector that is configured to generate an indication of a selected harmonic. The harmonic is selected based on a variable gain setting determined from among a plurality of gain settings or from a range of gain settings. Based on the selected harmonic, a mixer generates an output signal. A baseband signal or an intermediate signal is generated from the output signal.

公开(公告)号：US20140179251A1

公开(公告)日：2014-06-26

申请号：US13725151

申请日：2012-12-21

Applicant: QUALCOMM INCORPORATED

Inventor： Charles J. Persico ,  Jeremy D. Dunworth

IPC: H04B1/16

CPC classification number: H04B1/16 ,  H03D3/004 ,  H03D7/165 ,  H03G3/3052 ,  H03G3/3078 ,  H03J7/04 ,  H04W52/029 ,  Y02D70/142 ,  Y02D70/23 ,  Y02D70/40

Abstract: A method of harmonic selection for mixing with a received signal includes receiving a radio frequency (RF) signal and determining a variable gain setting from among a plurality of gain settings or from a range of gain settings. The variable gain setting is based on the RF signal. The method further includes selecting a harmonic to provide to an input of a mixer to generate an output signal. A baseband signal or an intermediate frequency signal is generated from the output signal. The harmonic is selected based on the variable gain setting. An apparatus includes a harmonic selector that is configured to generate an indication of a selected harmonic. The harmonic is selected based on a variable gain setting determined from among a plurality of gain settings or from a range of gain settings. Based on the selected harmonic, a mixer generates an output signal. A baseband signal or an intermediate signal is generated from the output signal.

Abstract translation: 用于与接收信号混合的谐波选择的方法包括从多个增益设置或从增益设置的范围接收射频（RF）信号和确定可变增益设置。 可变增益设置基于RF信号。 该方法还包括选择谐波以提供给混频器的输入端以产生输出信号。 从输出信号生成基带信号或中频信号。 根据可变增益设置选择谐波。 一种装置包括被配置为产生所选谐波的指示的谐波选择器。 基于从多个增益设置中确定的可变增益设置或从增益设置的范围来选择谐波。 基于所选择的谐波，混频器产生输出信号。 从输出信号产生基带信号或中间信号。

公开(公告)号：US08884672B2

公开(公告)日：2014-11-11

申请号：US13705023

申请日：2012-12-04

Applicant: QUALCOMM Incorporated

Inventor： Gary John Ballantyne ,  Jeremy D. Dunworth ,  Bhushan Shanti Asuri

IPC: H03L7/00 ,  H03L7/085 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/085 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093

Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Abstract translation: 锁相环（PLL）器件可配置在模拟锁相环和混合模拟数字锁相环路中。 在模拟模式中，至少相位检测器，模拟环路滤波器和压控振荡器（VCO）被连接以形成模拟环路。 在数字模式下，连接至少相位检测器，压控振荡器（VCO），时间数字转换器（TDC），数字环路滤波器和数模转换器（DAC），以形成混合数字模拟 循环。

公开(公告)号：US08531219B1

公开(公告)日：2013-09-10

申请号：US13866871

申请日：2013-04-19

Applicant: QUALCOMM Incorporated

Inventor： Jeremy D. Dunworth ,  Gary J. Ballantyne ,  Bhushan S. Asuri ,  Jifeng Geng ,  Gurkanwal S. Sahota

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/093

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract translation: 在锁相环（PLL）处执行数据信号的调制的方法包括至少部分地基于数据信号在PLL的高频端口生成数字环路信号。 该方法还包括区分数字环路信号以产生数字输入信号并将数字输入信号转换为模拟电流信号。 基于模拟电流信号产生第一反馈信号。 该方法还包括在PLL的较低频率端口处产生基于第一反馈信号的第二反馈信号，并且还基于该数据信号。 根据另外的实施例，公开了装置和计算机可读介质。

公开(公告)号：US20130181756A1

公开(公告)日：2013-07-18

申请号：US13705023

申请日：2012-12-04

Applicant: QUALCOMM Incorporated

Inventor： Gary John Ballantyne ,  Jeremy D. Dunworth ,  Bhushan Shanti Asuri

IPC: H03L7/085

CPC classification number: H03L7/085 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093

Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Abstract translation: 锁相环（PLL）器件可配置在模拟锁相环和混合模拟数字锁相环路中。 在模拟模式中，至少相位检测器，模拟环路滤波器和压控振荡器（VCO）被连接以形成模拟环路。 在数字模式下，连接至少相位检测器，压控振荡器（VCO），时间数字转换器（TDC），数字环路滤波器和数模转换器（DAC），以形成混合数字模拟 循环。