公开(公告)号：US09645591B2

公开(公告)日：2017-05-09

申请号：US14151701

申请日：2014-01-09

Applicant: QUALCOMM Incorporated

Inventor： Masoud Roham ,  Wei Zheng ,  Liang Dai ,  Dinesh J. Alladi ,  Yuhua Guo

IPC: G05F1/56 ,  G05F1/575

CPC classification number: G05F1/56 ,  G05F1/575

Abstract: Exemplary embodiments are related to voltage regulators. A device may include a first energy storage element coupled between a ground voltage and an output. The device may also include a second energy storage element coupled to the ground voltage and configured to selectively couple to the output. Further, the device may include a voltage regulator coupled between an input and the second energy storage element.

公开(公告)号：US20140247170A1

公开(公告)日：2014-09-04

申请号：US13782335

申请日：2013-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： Karthik Nagarajan ,  Dinesh J. Alladi

IPC: H03M1/12

CPC classification number: H03M1/0604 ,  G06F1/3296 ,  H03M1/00 ,  H03M1/46 ,  Y02D10/172

Abstract: A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage. The apparatus consists of a common mode voltage and regulator correction module. The common mode voltage and regulator correction module includes a phase frequency detector, a charge pump and may include a transconductance cell.

Abstract translation: 用于控制逐次逼近寄存器模数转换器和比较器共模电压的电源电压的方法和装置。 该方法包括：测量逐次逼近寄存器转换时间; 将逐次逼近寄存器转换时间与期望的转换时间进行比较; 并且如果需要，执行供电和/或比较器共模电压中的至少一个的闭环调节。 该装置由共模电压和调节器校正模块组成。 共模电压和调节器校正模块包括相位频率检测器，电荷泵，并且可以包括跨导单元。

公开(公告)号：US20140253210A1

公开(公告)日：2014-09-11

申请号：US13787590

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Omid Rajaee ,  Wei Zheng ,  Dinesh J. Alladi ,  Yuhua Guo

IPC: H03K5/156 ,  H03K3/012 ,  H03L5/00

CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/35613 ,  H03K19/01714 ,  H03K19/018521 ,  H03L5/00

Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

Abstract translation: 本公开的某些方面提供了采用低等待时间交流耦合升压电路的电压电平移位电路，以及包括这种电平转换电路的其它电路和装置。 与常规电平转换器相比，这种电平移位电路提供显着更低的等待时间（例如，延迟减少至少两倍）。 与模拟角相比，提供一致的延迟，与此相比，电平移位电路与常规电平转换器相比，也提供了显着更低的功耗和减少的占空比失真。

公开(公告)号：US20150116020A1

公开(公告)日：2015-04-30

申请号：US14065854

申请日：2013-10-29

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Dinesh J. Alladi

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/356034 ,  H03K3/356069

Abstract: The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.

Abstract translation: 本公开包括用于锁存信号的电路和方法。 在一个实施例中，两个逆变器被背靠背配置以锁定信号。 每个逆变器包括配置在逆变器晶体管的控制端之间的电容器。 在一个实施例中，电路是比较器的一部分。 第一和第二电压被接收在差分晶体管的控制端上，并且差分输出信号耦合到两个背靠背的反相器。 在一个实施例中，电路被禁用，并且反相器中的晶体管的控制端子上的电压被设置为低于诸如电源的参考值，以增加电路的速度。