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公开(公告)号：US12051979B2
公开(公告)日：2024-07-30
申请号：US17755574
申请日：2021-01-05
Inventor： Ryusuke Kanomata , Yusuke Kinoshita , Hidetoshi Ishida
CPC classification number: H02M3/33584 , H02M1/0058 , H01L27/0629 , H02M1/08 , H02M3/155
Abstract: A substrate electric potential stabilization circuit is configured to be connected to a bidirectional switch element including a first main electrode, a second main electrode, and a backside electrode. The stabilization circuit includes a first switch connected to the first main electrode and the backside electrode in series between the first main electrode and the backside electrode, a second switch connected to the second main electrode and the backside electrode in series between the second main electrode and the backside electrode, and a through-current prevention circuit configured to prevent the first switch and the second switch from being turned on simultaneously. The substrate electric potential stabilization circuit prevents a through-current flowing in this circuit.
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公开(公告)号：US09837496B2
公开(公告)日：2017-12-05
申请号：US14930628
申请日：2015-11-02
Inventor： Yusuke Kinoshita , Satoshi Tamura , Tetsuzo Ueda
IPC: H01L29/06 , H01L29/205 , H01L29/66 , H01L29/778 , H01L29/808 , H01L29/43 , H01L29/10 , H01L29/20 , H01L29/201
CPC classification number: H01L29/205 , H01L29/1066 , H01L29/2003 , H01L29/201 , H01L29/432 , H01L29/66462 , H01L29/66916 , H01L29/66924 , H01L29/7786 , H01L29/8086
Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0≦p+q≦1, 0≦p, and 0≦q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0≦r+s≦1, 0≦r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0≦t+u≦1, 0≦t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0≦x+y≦1, 0≦x, and 0≦y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.
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公开(公告)号：US12191846B2
公开(公告)日：2025-01-07
申请号：US17904384
申请日：2021-02-16
Inventor： Yusuke Kinoshita , Hidetoshi Ishida
IPC: H03K17/082 , H03K17/0812 , H03K17/687
Abstract: Provided are a determination device and a switch system capable of suppressing a power loss of a semiconductor switch. Determination device is used for semiconductor switch. Semiconductor switch includes junction field-effect transistor having gate and source corresponding to gate. Determination device includes resistor and determination circuit. Resistor has a first end and a second end. The first end of resistor is connected to gate. Determination circuit determines that overcurrent is flowing through semiconductor switch when there is a predetermined change in gate-source voltage of junction field-effect transistor in a range smaller than gate drive voltage provided between the second end of resistor and source.
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公开(公告)号：US11736104B2
公开(公告)日：2023-08-22
申请号：US17633160
申请日：2020-10-23
Inventor： Yusuke Kinoshita , Hidetoshi Ishida , Hiroyuki Handa , Yuji Kudoh , Satoshi Nakazawa
IPC: H03K3/00 , H03K17/687 , G01R31/26
CPC classification number: H03K17/687 , G01R31/2621
Abstract: A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.
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公开(公告)号：US12191848B2
公开(公告)日：2025-01-07
申请号：US17916743
申请日：2021-04-05
Inventor： Ryosuke Maeda , Yusuke Kinoshita , Hidetoshi Ishida
Abstract: A control circuit controls a switching element including a gate and a source corresponding to the gate. The control circuit includes an inductor, a circuit element, and a resistor. The inductor is connected between the gate and the source of the switching element. The circuit element is connected in series to the inductor between the gate and the source. The circuit element allows an electric current to flow therethrough in response to generation of electromotive force in the inductor. The resistor is connected in parallel to the inductor and the circuit element between the gate and the source.
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Patent Agency Ranking
公开(公告)号：US12126274B2
公开(公告)日：2024-10-22
申请号：US17290489
申请日：2019-08-23
Inventor： Yusuke Kinoshita , Yasuhiro Yamada , Takashi Ichiryu , Masanori Nomura , Hidetoshi Ishida
IPC: H02M7/483 , H01L29/778 , H02M1/08
CPC classification number: H02M7/483 , H01L29/7786 , H02M1/08
Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0≤x1
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公开(公告)号：US12125904B2
公开(公告)日：2024-10-22
申请号：US17612542
申请日：2020-05-14
Inventor： Takashi Ichiryu , Yusuke Kinoshita , Ryusuke Kanomata , Masanori Nomura , Hidetoshi Ishida
IPC: H01L29/778 , H01L23/00 , H01L25/07 , H01L27/06 , H01L27/07 , H01L29/10 , H01L29/20 , H01L29/205 , H01L29/417 , H01L29/423 , H03K17/12 , H03K17/687
CPC classification number: H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/205
Abstract: A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.
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公开(公告)号：US11791803B2
公开(公告)日：2023-10-17
申请号：US17626296
申请日：2020-07-10
Inventor： Yusuke Kinoshita , Takashi Ichiryu , Hidetoshi Ishida
Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
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公开(公告)号：US11637552B2
公开(公告)日：2023-04-25
申请号：US17614716
申请日：2020-04-28
Inventor： Yusuke Kinoshita , Takashi Ichiryu , Ryusuke Kanomata , Hidetoshi Ishida
Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.
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公开(公告)号：US11257733B2
公开(公告)日：2022-02-22
申请号：US16497744
申请日：2018-03-27
Inventor： Takashi Ichiryu , Masanori Nomura , Yusuke Kinoshita , Hidetoshi Ishida , Yasuhiro Yamada
IPC: H01L23/367 , H01L23/29 , H01L23/31 , H01L23/373 , H01L23/532 , H01L23/00
Abstract: A semiconductor device includes a supporting substrate, a semiconductor chip, a resin member, and a heat-dissipating metal layer. The supporting substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the supporting substrate. The semiconductor chip includes a plurality of electrodes. The semiconductor chip is bonded to the supporting substrate on one side thereof with the first surface. The resin member has a first surface and a second surface located opposite from each other in a thickness direction defined for the resin member. The resin member covers at least a side surface of the supporting substrate and a side surface of the semiconductor chip. The heat-dissipating metal layer is arranged in contact with the supporting substrate and the resin member to cover the second surface of the supporting substrate and the second surface of the resin member at least partially.
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