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Patent Agency Ranking
公开(公告)号：US09141470B2
公开(公告)日：2015-09-22
申请号：US14110697
申请日：2013-03-05
Applicant: PANASONIC CORPORATION
Inventor： Naoya Yosoku , Hiroyuki Yoshikawa , Hiroyuki Motozuka
CPC classification number: G06F11/10 , H03M13/1117 , H03M13/1137 , H03M13/3715 , H03M13/6527 , H03M13/6577 , H03M13/658
Abstract: A decoding device has a decoding section that has a plurality of decoding cores which decode a received packet (e.g., likelihoods generated as a result of demodulation), which will become data to be decoded, in parallel on a per-likelihood basis and in which a first decoding core and a second decoding core of a plurality of decoding cores can perform decoding in parallel and a control section that controls decoding, wherein the decoding section lets the second decoding core decode a second likelihood when the second likelihood is input in the middle of the first decoding core decoding the first likelihood of the data to be decoded, whereby another likelihood can be decoded by use of another decoding core in the middle of decoding of a certain likelihood. Thus, entire decoding speed is increased.
Abstract translation: 解码装置具有解码部分，其具有多个解码核，其解码接收的分组（例如，作为解调结果生成的似然性），其将成为将被解码的数据，并且基于每个可能性，并且其中 多个解码核心的第一解码核心和第二解码核心可以并行地执行解码，以及控制解码部分，其中当第二可能性在中间输入时，解码部分使第二解码核心解码第二似然 第一解码核心解码要解码的数据的第一可能性，从而在某种可能性的解码的中间通过使用另一个解码核心来解码另一似然。 因此，整个解码速度增加。
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公开(公告)号：US09912786B2
公开(公告)日：2018-03-06
申请号：US14110382
申请日：2013-02-27
Applicant: PANASONIC CORPORATION
Inventor： Naoya Yosoku , Hiroyuki Yoshikawa , Naganori Shirakata
CPC classification number: H04L69/22 , H03M13/1111 , H03M13/6325 , H03M13/6527 , H04L1/005 , H04L1/0057 , H04L1/0063 , H04L1/0072 , H04L25/03057
Abstract: A demodulation section demodulates a received signal. A decoding section decodes an output from the demodulation section. A buffer temporarily stores a portion of the received signal. A header analyzing section gives the buffer timing at which demodulation and decoding of a payload of the received signal are initiated, on the basis of a result of combination of a plurality of header sequences included in a header of the received signal and results of processing of the demodulation section and the decoding section. An improved SNR is achieved by means of combination of the plurality of header sequences, so that an iterative decoding count used for decoding the header become smaller.
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公开(公告)号：US09838036B2
公开(公告)日：2017-12-05
申请号：US15011709
申请日：2016-02-01
Applicant: Panasonic Corporation
Inventor： Hiroyuki Motozuka , Hiroyuki Yoshikawa
CPC classification number: H03M13/1122 , H03M13/6502 , H03M13/6561 , H04L1/0009 , H04L1/0052 , H04L1/0057
Abstract: A storage which, in operation, stores a first minimum value and a second minimum value each time a plurality of data are input. Round-robin comparison circuitry which, in operation, makes a magnitude comparison among the plurality of data. First selection comparison circuitry and second selection comparison circuitry which, in operation, make a magnitude comparison between the first minimum value and each of the plurality of data and a magnitude comparison between the second minimum value and each of the plurality of data, respectively. Judgment circuitry which, in operation, judges a new first minimum value and a new second minimum value on the basis of a comparison result from the round-robin comparison circuitry and comparison results from the first and second selection comparison circuitry.
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4.发明授权公开(公告)号：US09491030B2
公开(公告)日：2016-11-08
申请号：US14607333
申请日：2015-01-28
Applicant: Panasonic Corporation
Inventor： Hiroyuki Yoshikawa , Yoshinori Shirakawa , Takenori Sakamoto , Koichiro Tanaka
CPC classification number: H04L27/3863 , H04L27/3488
Abstract: A phase rotation correcting method includes receiving a signal modulated by a multi-value modulation method; recognizing a position of a symbol point of the received signal on an IQ plane; performing phase rotation for rotating a phase of the symbol point of the received signal toward an I axis or a Q axis in accordance with the recognized position and calculating, as an amount of phase rotation correction, a value on an axis different from the axis toward which the phase of the symbol point has been rotated by the phase rotation; and correcting phase rotation of the symbol point by using the calculated amount of phase rotation correction.
Abstract translation: 相位旋转校正方法包括：接收由多值调制方式调制的信号; 识别接收信号的符号点在IQ平面上的位置; 执行相位旋转，以根据识别的位置将接收信号的符号点的相位朝向I轴或Q轴旋转，并且将相对于旋转校正的轴计算为不同于轴的轴上的值 符号点的相位已被相位旋转旋转; 以及通过使用所计算的相位旋转校正量校正符号点的相位旋转。
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公开(公告)号：US20140082455A1
公开(公告)日：2014-03-20
申请号：US14110697
申请日：2013-03-05
Applicant: PANASONIC CORPORATION
Inventor： Naoya Yosoku , Hiroyuki Yoshikawa , Hiroyuki Motozuka
IPC: G06F11/10
CPC classification number: G06F11/10 , H03M13/1117 , H03M13/1137 , H03M13/3715 , H03M13/6527 , H03M13/6577 , H03M13/658
Abstract: A decoding device has a decoding section that has a plurality of decoding cores which decode a received packet (e.g., likelihoods generated as a result of demodulation), which will become data to be decoded, in parallel on a per-likelihood basis and in which a first decoding core and a second decoding core of a plurality of decoding cores can perform decoding in parallel and a control section that controls decoding, wherein the decoding section lets the second decoding core decode a second likelihood when the second likelihood is input in the middle of the first decoding core decoding the first likelihood of the data to be decoded, whereby another likelihood can be decoded by use of another decoding core in the middle of decoding of a certain likelihood. Thus, entire decoding speed is increased.
Abstract translation: 解码装置具有解码部分，其具有多个解码核，其解码接收的分组（例如，作为解调结果生成的似然性），其将成为将被解码的数据，并且基于每个可能性，并且其中 多个解码核心的第一解码核心和第二解码核心可以并行地执行解码，以及控制解码部分，其中当第二可能性在中间输入时，解码部分使第二解码核心解码第二似然 第一解码核心解码要解码的数据的第一可能性，从而在某种可能性的解码的中间通过使用另一个解码核心来解码另一似然。 因此，整个解码速度增加。
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