公开(公告)号：US20230100196A1

公开(公告)日：2023-03-30

申请号：US18071876

申请日：2022-11-30

Applicant: POSTECH Research and Business Development Foundation

Inventor： Rock Hyun BAEK ,  Jun Sik YOON ,  Jin Su JEONG ,  Seung Hwan LEE

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

公开(公告)号：US20220277189A1

公开(公告)日：2022-09-01

申请号：US17551450

申请日：2021-12-15

Applicant: RESEARCH COOPERATION FOUNDATION OF YEUNGNAM UNIVERSITY ,  POSTECH Research and Business Development Foundation

Inventor： Hyun Chul CHOI ,  Rock Hyun BAEK ,  Jun Sik YOON ,  Hyeok YUN

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G03F7/20

Abstract: A method for setting of a semiconductor manufacturing parameter according to an embodiment is a method performed in a computing device including one or more processors, and a memory for storing one or more programs executed by the one or more processors, the method including an operation of inputting manufacturing parameters for manufacturing a semiconductor to a neural network model and an operation of training the neural network model to predict at least one of power and delay of the semiconductor based on the input manufacturing parameters.

公开(公告)号：US20200243644A1

公开(公告)日：2020-07-30

申请号：US16750292

申请日：2020-01-23

Applicant: POSTECH Research and Business Development Foundation

Inventor： Rock Hyun BAEK ,  Jun Sik YOON ,  Jin Su JEONG ,  Seung Hwan LEE

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: Disclosed is a field effect transistor including an insulating film disposed between a source/drain region and a substrate. Since the insulating film prevents current leakage under a channel, it is not necessary to form a punch-through stopper. Further disclosed is a method of forming a field effect transistor.

公开(公告)号：US20220085781A1

公开(公告)日：2022-03-17

申请号：US17387876

申请日：2021-07-28

Applicant: POSTECH Research and Business Development Foundation

Inventor： Rock Hyun BAEK ,  Jun Sik YOON

IPC: H03G3/30 ,  H03F3/21 ,  H03F3/193 ,  H03F3/45

Abstract: Disclosed in a CASCODE device in which multiple transistors are stacked in a vertical direction and connected in series. The CASCODE device exhibits improvements in device/circuit intrinsic gain (GmRo) that is a performance index for analog/RF applications, cutoff frequency (Ft), and maximum oscillation frequency (Fmax). A method of manufacturing the CASCODE device is also disclosed.