公开(公告)号：US20230422529A1

公开(公告)日：2023-12-28

申请号：US18102612

申请日：2023-01-27

Applicant: POSTECH Research and Business Development Foundation

Inventor： Byoung Hun LEE ,  Yong Su LEE

IPC: H10K10/46

CPC classification number: H10K10/486 ,  H10K10/466

Abstract: Disclosed herein are a multi-level device which has a ternary characteristic and can reduce hysteresis, and a method of manufacturing the same. The multi-level device can have a plurality of turn-on voltages, that is, a plurality of threshold voltages, thereby providing multi-level conductivity as a ternary device characteristic. In addition, a double insulating layer made of a dielectric layer and an organic polymer layer is used as a separation layer for channel layer separation, and by removing the hysteresis due to a trap charge at an interface between a channel layer and an insulating layer, a uniform ternary characteristic can always be maintained, and by forming the channel layer on an organic polymer layer, the channel layer can be more stably formed on the insulating layer.

公开(公告)号：US20240099136A1

公开(公告)日：2024-03-21

申请号：US18470288

申请日：2023-09-19

Applicant: POSTECH Research and Business Development Foundation

Inventor： Byoung Hun LEE ,  Hyeon Jun HWANG

IPC: H10N10/01 ,  H10N10/855

CPC classification number: H10N10/01 ,  H10N10/855

Abstract: Disclosed herein are a method for manufacturing a graphene thermoelectric device and a graphene thermoelectric device manufactured thereby. The method for manufacturing a graphene thermoelectric device includes: forming a graphene channel layer on a substrate; forming a thermoelectric structure by depositing a first electrode and a second electrode on both ends of the graphene channel layer; and doping the graphene channel layer by dipping the thermoelectric structure into a doping solution.

公开(公告)号：US20240347643A1

公开(公告)日：2024-10-17

申请号：US18632104

申请日：2024-04-10

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Byoung Hun LEE ,  Yongsu LEE ,  Hae-Won LEE

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L29/66742

Abstract: An anti-ambipolar transistor in which a turn-on operation is performed at a specific gate voltage and a method of manufacturing the same are disclosed. A vertically stacked structure including a first semiconductor layer and a second semiconductor layer, which are disposed perpendicular to the surface of a substrate, is formed, and then a gate dielectric layer and a gate electrode, which completely surround the side of the vertically stacked structure, are formed. Through the vertical structure, an electric field is generated in a direction parallel to the substrate, and a drain-source current is applied in a direction perpendicular to the surface of the substrate. This ensures the integration of the transistor and efficient operation of the transistor.