MULTI-LEVEL DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20230422529A1

    公开(公告)日:2023-12-28

    申请号:US18102612

    申请日:2023-01-27

    CPC classification number: H10K10/486 H10K10/466

    Abstract: Disclosed herein are a multi-level device which has a ternary characteristic and can reduce hysteresis, and a method of manufacturing the same. The multi-level device can have a plurality of turn-on voltages, that is, a plurality of threshold voltages, thereby providing multi-level conductivity as a ternary device characteristic. In addition, a double insulating layer made of a dielectric layer and an organic polymer layer is used as a separation layer for channel layer separation, and by removing the hysteresis due to a trap charge at an interface between a channel layer and an insulating layer, a uniform ternary characteristic can always be maintained, and by forming the channel layer on an organic polymer layer, the channel layer can be more stably formed on the insulating layer.

    ANTI-AMBIPOLAR TRANSISTOR HAVING VERTICAL STRUCTURE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20240347643A1

    公开(公告)日:2024-10-17

    申请号:US18632104

    申请日:2024-04-10

    CPC classification number: H01L29/78642 H01L29/66742

    Abstract: An anti-ambipolar transistor in which a turn-on operation is performed at a specific gate voltage and a method of manufacturing the same are disclosed. A vertically stacked structure including a first semiconductor layer and a second semiconductor layer, which are disposed perpendicular to the surface of a substrate, is formed, and then a gate dielectric layer and a gate electrode, which completely surround the side of the vertically stacked structure, are formed. Through the vertical structure, an electric field is generated in a direction parallel to the substrate, and a drain-source current is applied in a direction perpendicular to the surface of the substrate. This ensures the integration of the transistor and efficient operation of the transistor.

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