公开(公告)号：US20250077854A1

公开(公告)日：2025-03-06

申请号：US18652689

申请日：2024-05-01

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Seyoung KIM ,  Doyoon KIM

IPC: G06N3/065 ,  G06N3/08

Abstract: A digital-analog memory integrated deep learning accelerator system may include: a main digital device including a first array, the first array having digital circuits and configured to store weights for on-chip learning; an analog device including a second array, the second array having analog circuits and configured to update and store gradient information about the weights during the on-chip learning; and a sub-digital device including a third array, the third array having digital circuits and configured to store values read from the second array and to transfer a value exceeding a threshold to the first array. The digital-analog memory integrated deep learning accelerator system may perform a matrix-level learning process through an array set including the first array, the second array, and the third array. An artificial neural network learning method for a digital-analog memory integrated deep learning accelerator system is also disclosed.

公开(公告)号：US20250077855A1

公开(公告)日：2025-03-06

申请号：US18817862

申请日：2024-08-28

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Seyoung KIM ,  Seungkun KIM ,  Jeonghoon SON

IPC: G06N3/065 ,  G11C11/54 ,  H10N70/00 ,  H10N70/20

Abstract: The present disclosure relates to a double gate neuromorphic memory device and a manufacturing method thereof. The double gate neuromorphic memory device is an electrochemical device, and includes a bottom gate provided on an upper portion of a semiconductor substrate, a channel area surrounding the upper portion and side surfaces of the bottom gate, a source electrode and a drain electrode provided in contact with both sides of the channel area, and a top gate provided on an upper portion of a channel area between the source electrode and the drain electrode.

公开(公告)号：US20230047277A1

公开(公告)日：2023-02-16

申请号：US17871855

申请日：2022-07-22

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seyoung KIM ,  Doyoon KIM ,  Hyunjeong KWAK ,  Jeonghoon SON ,  Chuljun LEE

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/04

Abstract: Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.

公开(公告)号：US20240220784A1

公开(公告)日：2024-07-04

申请号：US18381273

申请日：2023-10-18

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seyoung KIM ,  Doyoon KIM

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: A synaptic array device according to one embodiment of the present disclosure comprises a first synaptic array representing weight values, a second synaptic array receiving the error gradient of the weights of the first synaptic array and representing gradient values refined in row units, and a third synaptic array receiving the gradient values refined in row units from the second synaptic array and passing the portion of the received gradient values exceeding a threshold to the first synaptic array, wherein the third synaptic array derives a moving average value by averaging accumulated values of the gradient values received from the second synaptic array and passes the derived moving average value to the second synaptic array.

公开(公告)号：US20250104787A1

公开(公告)日：2025-03-27

申请号：US18885111

申请日：2024-09-13

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Seyoung KIM ,  Byoungwoo LEE ,  Jeonghoon SON ,  Seungkun KIM

IPC: G11C27/00 ,  G06N3/065 ,  H10B63/00 ,  H10N70/20

Abstract: The present disclosure relates to a three-terminal synaptic device for artificial neural network learning, a synaptic array using the same, and a method of operating the same. The three-terminal synaptic device includes a first transistor; an electrochemical memory (ECRAM) connected in parallel to the first transistor; and a second transistor connected in series to the parallel structure. Accordingly, the present disclosure can achieve an accuracy improvement of inference and learning operations in an artificial neural network through parallel operation by configuring a cross-point array based on the synaptic device with the three-terminal structure comprised of the electrochemical memory and two transistors.

公开(公告)号：US20230195363A1

公开(公告)日：2023-06-22

申请号：US17837006

申请日：2022-06-09

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seyoung KIM ,  Kyungmi NOH ,  Chaeun LEE ,  Wonjae JI

IPC: G06F3/06 ,  G06N3/063

CPC classification number: G06F3/0655 ,  G06N3/063 ,  G06F3/0604 ,  G06F3/0673

Abstract: According to an embodiment of the present disclosure, a neuromorphic semiconductor device includes a first synaptic array that includes a first synaptic device having a first weight, a second synaptic array that includes a second synaptic device configured to symmetrically adjust a second weight with respect to a potentiation or depression operation, and a control unit that configures a single synapse through the first synaptic device and the second synaptic device and determines a final weight by accessing the first and second weights together in a reading process.