公开(公告)号：US20230047277A1

公开(公告)日：2023-02-16

申请号：US17871855

申请日：2022-07-22

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seyoung KIM ,  Doyoon KIM ,  Hyunjeong KWAK ,  Jeonghoon SON ,  Chuljun LEE

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/04

Abstract: Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.