公开(公告)号：US20180122939A1

公开(公告)日：2018-05-03

申请号：US15854220

申请日：2017-12-26

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tomonari OTA ,  Shigetoshi SOTA ,  Eiji YASUDA ,  Takeshi IMAMURA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Kazuma YOSHIDA ,  Masaaki HIRAKO ,  Dohwan AHN

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/823475 ,  H01L21/823487 ,  H01L24/47 ,  H01L27/088 ,  H01L29/41741 ,  H01L29/4238

Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.