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公开(公告)号:US11916763B2
公开(公告)日:2024-02-27
申请号:US17620815
申请日:2019-07-01
发明人: Yuta Ukon , Shuhei Yoshida , Shoko Oteru , Namiko Ikeda , Koyo Nitta
IPC分类号: H04L43/026 , H04L45/7453
CPC分类号: H04L43/026 , H04L45/7453
摘要: A traffic monitoring apparatus includes: a header analysis circuit configured to acquire one or more identifiers from a header of a received packet; a rule registration circuit configured to convert a rule table including rules in which one or more rule elements are registered for each of the rules into a predetermined format and register the rule table in a rule matching circuit; and the rule matching circuit configured to search for rules to be matched with the acquired identifiers.
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2.
公开(公告)号:US11683255B2
公开(公告)日:2023-06-20
申请号:US17604943
申请日:2019-05-14
发明人: Shuhei Yoshida , Yuta Ukon , Shoko Oteru , Namiko Ikeda , Koyo Nitta
IPC分类号: H04L43/12 , H04L43/0811 , H04L43/0829 , H04L43/0823 , H04L43/0882
CPC分类号: H04L43/12 , H04L43/0811 , H04L43/0829 , H04L43/0847 , H04L43/0882
摘要: An embodiment packet capture device comprises: a packet receiver configured to receive a packet from a network; a packet retainer configured to store the received packet in a memory to temporarily retain the received packet; a failure detector configured to determine a communication failure is present in the network; a capture controller configured to determine an operation stop address such that retention of packets from the network in time periods before and after a detection time point of the communication failure is ensured when the communication failure is detected by the failure detector; and a capture data generator configured to output the packet stored in the memory as capture data when a storage destination address of the packet stored in the memory has reached the operation stop address or when at least a predetermined waiting time period has elapsed from the detection time point of the communication failure.
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公开(公告)号:US20220263733A1
公开(公告)日:2022-08-18
申请号:US17628954
申请日:2019-07-23
发明人: Shuhei Yoshida , Yuta Ukon , Shoko Oteru , Namiko Ikeda , Koyo Nitta
IPC分类号: H04L43/026 , H04L69/22 , H04L43/18 , H04L43/16 , H04L43/04
摘要: A burst traffic detection device includes a packet receiver configured to receive packets from a network, a flow specification device configured to specify, in accordance with header information of the packets, flow rules, a flow information storage device configured to store flow information of the specified flow rules, a statistical information storage device configured to store statistical information including the total number of packets for each flow rule and/or the total number of bytes for each flow rule, a burst detection device configured to detect the occurrence of burst traffic in accordance with the statistical information, and a detection count storage device configured to store the number of times of the occurrence of burst traffic.
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公开(公告)号:US20230009530A1
公开(公告)日:2023-01-12
申请号:US17783540
申请日:2019-12-11
发明人: Shoko Oteru , Shuhei Yoshida , Yuta Ukon , Namiko Ikeda , Koyo Nitta
IPC分类号: H04L47/34 , H04L49/901 , H04L1/16
摘要: An embodiment is a data sequence correction method. The data sequence correction method including temporarily saving data with sequence information imparted thereto in a ring buffer, the ring buffer having a predetermined number of storage regions corresponding to the sequence information, and being provided with a monitoring section made up of one, or two or more consecutive sequence numbers, and an acceptance section in which a start or a second sequence number of the monitoring section is a start sequence number, and the sequence number ahead by a count of storage regions of the ring buffer including the start of the monitoring section is an end sequence number.
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公开(公告)号:US20210116882A1
公开(公告)日:2021-04-22
申请号:US17251739
申请日:2019-05-21
发明人: Syuhei Yoshida , Yuta Ukon , Koji Yamazaki , Koyo Nitta
IPC分类号: G05B19/4097
摘要: An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.
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6.
公开(公告)号:US10891246B2
公开(公告)日:2021-01-12
申请号:US16490393
申请日:2018-02-28
发明人: Yuta Ukon , Syuhei Yoshida , Koji Yamazaki
摘要: A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.
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公开(公告)号:US12010045B2
公开(公告)日:2024-06-11
申请号:US17440241
申请日:2020-04-08
发明人: Tomoaki Kawamura , Shoko Oteru , Yuta Ukon , Shuhei Yoshida
IPC分类号: H04L49/9057 , H04L49/9047
CPC分类号: H04L49/9057 , H04L49/9047
摘要: The packet processing apparatus includes a packet memory, a transmission processing unit that writes a plurality of packets to be transmitted to the packet memory to generate a combination packet into which the plurality of packets have been concatenated, a line handling unit that sends packets to a communication line, and a combination packet transfer unit that DMA-transfers the combination packet from the packet memory to the line handling unit. The transmission processing unit writes information on an address in the packet memory of beginning data of an individual packet in the combination packet to a descriptor. The line handling unit separates the DMA-transferred combination packet into a plurality of packets and sends the plurality of packets to the communication line.
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公开(公告)号:US11882061B2
公开(公告)日:2024-01-23
申请号:US17619189
申请日:2019-06-24
发明人: Shoko Oteru , Shuhei Yoshida , Yuta Ukon , Namiko Ikeda , Koyo Nitta
IPC分类号: H04L49/9057 , H04L1/1607 , H04L47/28 , H04L47/34 , H04L49/55
CPC分类号: H04L49/9057 , H04L1/1621 , H04L47/28 , H04L47/34 , H04L49/557
摘要: A data sequence correction method for temporarily saving data with sequence information in a ring buffer and performing sequence correction is provided. The ring buffer includes a number of storage regions, a monitoring section having one or more continuous sequence numbers, and an acceptance section having a first or second sequence number of the monitoring section as a start sequence number and a sequence number immediately preceding the start sequence number of the monitoring section as an end sequence number. The method includes, when a value determined based on a remainder obtained by dividing a sequence number of received data by the number of storage regions is inside the acceptance section, writing the received data in a position of the storage region corresponding to the determined value, and when data are written in the entire monitoring section, reading out all the data in the monitoring section.
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公开(公告)号:US11374874B2
公开(公告)日:2022-06-28
申请号:US17290342
申请日:2019-10-23
发明人: Yuta Ukon , Shuhei Yoshida , Koyo Nitta
IPC分类号: H04L47/80 , H04L47/6275
摘要: An access control unit includes packet buffers provided for each of users, a packet identification unit that stores received packets in a corresponding packet buffer, a scheduling unit that decides a packet buffer to be the object of transfer, a transfer control unit that, in a case that updating of reference data can be performed at an application processing circuit, and also the packet buffer decided by the scheduling unit is different from the current packet buffer that is the object of transfer, updates to reference data corresponding to the packet buffer decided by the scheduling unit, and a buffer selection unit that connects the packet buffers decided to be the object of transfer to the packet transfer unit when updating of reference data is completed.
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公开(公告)号:US20210409344A1
公开(公告)日:2021-12-30
申请号:US17290342
申请日:2019-10-23
发明人: Yuta Ukon , Shuhei Yoshida , Koyo Nitta
IPC分类号: H04L12/927 , H04L12/865
摘要: An access control unit includes packet buffers provided for each of users, a packet identification unit that stores received packets in a corresponding packet buffer, a scheduling unit that decides a packet buffer to be the object of transfer, a transfer control unit that, in a case that updating of reference data can be performed at an application processing circuit, and also the packet buffer decided by the scheduling unit is different from the current packet buffer that is the object of transfer, updates to reference data corresponding to the packet buffer decided by the scheduling unit, and a buffer selection unit that connects the packet buffers decided to be the object of transfer to the packet transfer unit when updating of reference data is completed.
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