Burst Traffic Detection Device and Method

    公开(公告)号:US20220263733A1

    公开(公告)日:2022-08-18

    申请号:US17628954

    申请日:2019-07-23

    摘要: A burst traffic detection device includes a packet receiver configured to receive packets from a network, a flow specification device configured to specify, in accordance with header information of the packets, flow rules, a flow information storage device configured to store flow information of the specified flow rules, a statistical information storage device configured to store statistical information including the total number of packets for each flow rule and/or the total number of bytes for each flow rule, a burst detection device configured to detect the occurrence of burst traffic in accordance with the statistical information, and a detection count storage device configured to store the number of times of the occurrence of burst traffic.

    Parameter Optimization Device, Method and Program

    公开(公告)号:US20210116882A1

    公开(公告)日:2021-04-22

    申请号:US17251739

    申请日:2019-05-21

    IPC分类号: G05B19/4097

    摘要: An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.

    Data processing apparatus, network system, packet order control circuit, and data processing method

    公开(公告)号:US10891246B2

    公开(公告)日:2021-01-12

    申请号:US16490393

    申请日:2018-02-28

    摘要: A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.

    Packet processing device and packet processing method

    公开(公告)号:US12010045B2

    公开(公告)日:2024-06-11

    申请号:US17440241

    申请日:2020-04-08

    IPC分类号: H04L49/9057 H04L49/9047

    CPC分类号: H04L49/9057 H04L49/9047

    摘要: The packet processing apparatus includes a packet memory, a transmission processing unit that writes a plurality of packets to be transmitted to the packet memory to generate a combination packet into which the plurality of packets have been concatenated, a line handling unit that sends packets to a communication line, and a combination packet transfer unit that DMA-transfers the combination packet from the packet memory to the line handling unit. The transmission processing unit writes information on an address in the packet memory of beginning data of an individual packet in the combination packet to a descriptor. The line handling unit separates the DMA-transferred combination packet into a plurality of packets and sends the plurality of packets to the communication line.

    Access control method, access control device, and data processing device

    公开(公告)号:US11374874B2

    公开(公告)日:2022-06-28

    申请号:US17290342

    申请日:2019-10-23

    IPC分类号: H04L47/80 H04L47/6275

    摘要: An access control unit includes packet buffers provided for each of users, a packet identification unit that stores received packets in a corresponding packet buffer, a scheduling unit that decides a packet buffer to be the object of transfer, a transfer control unit that, in a case that updating of reference data can be performed at an application processing circuit, and also the packet buffer decided by the scheduling unit is different from the current packet buffer that is the object of transfer, updates to reference data corresponding to the packet buffer decided by the scheduling unit, and a buffer selection unit that connects the packet buffers decided to be the object of transfer to the packet transfer unit when updating of reference data is completed.

    Access Control Method, Access Control Device, and Data Processing Device

    公开(公告)号:US20210409344A1

    公开(公告)日:2021-12-30

    申请号:US17290342

    申请日:2019-10-23

    IPC分类号: H04L12/927 H04L12/865

    摘要: An access control unit includes packet buffers provided for each of users, a packet identification unit that stores received packets in a corresponding packet buffer, a scheduling unit that decides a packet buffer to be the object of transfer, a transfer control unit that, in a case that updating of reference data can be performed at an application processing circuit, and also the packet buffer decided by the scheduling unit is different from the current packet buffer that is the object of transfer, updates to reference data corresponding to the packet buffer decided by the scheduling unit, and a buffer selection unit that connects the packet buffers decided to be the object of transfer to the packet transfer unit when updating of reference data is completed.