公开(公告)号：US20160043045A1

公开(公告)日：2016-02-11

申请号：US14920927

申请日：2015-10-23

申请人： Nam-Gyu BAEK ,  Young-Min LEE ,  Yun-Rae CHO ,  Sun-Dae KIM

发明人： Nam-Gyu BAEK ,  Young-Min LEE ,  Yun-Rae CHO ,  Sun-Dae KIM

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L24/03 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/08113 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection.

摘要翻译： 可用于半导体器件的焊盘结构可以包括绝缘层图案结构，插头和焊盘。 绝缘层图案结构具有插塞孔和至少一个通孔。 插头形成在插头孔中。 衬垫形成在绝缘层图案结构上。 垫与插头电连接，具有下表面和不平的上表面。 下表面包括插入通孔的突出部分。 不平坦的上表面包括凹部和升高部分，以提供高粗糙度和牢固的连接。

公开(公告)号：US20170103929A1

公开(公告)日：2017-04-13

申请号：US15201675

申请日：2016-07-05

申请人： Bo-Ra LEE ,  Jae-Ho JEONG ,  Nam-Gyu BAEK ,  Hyo-Seok WOO ,  Hyun-Sook YOON ,  Kwang-Yong LEE

发明人： Bo-Ra LEE ,  Jae-Ho JEONG ,  Nam-Gyu BAEK ,  Hyo-Seok WOO ,  Hyun-Sook YOON ,  Kwang-Yong LEE

IPC分类号： H01L21/66 ,  H01L27/115 ,  H01L23/00 ,  H01L29/423

CPC分类号： H01L22/34 ,  H01L23/562 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.