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公开(公告)号：US20170139016A1
公开(公告)日：2017-05-18
申请号：US15347872
申请日：2016-11-10
Applicant: NXP B.V.
Inventor： Klaus Reimann , Robert van Veldhoven , Jaap Ruigrok , Selcuk Ersoy , Ralf van Otten , Jörg Kock
CPC classification number: G01R33/0029 , G01R33/0017 , G01R33/0035 , G01R33/0082 , G01R33/096
Abstract: A magnetic field sensor is disclosed for providing an output signal in response to an external magnetic field. The sensor comprises a primary magnetic field transducer for producing a primary signal in response to the external magnetic field and having a first magnetic field saturation characteristic; a secondary magnetic field transducer for producing a secondary signal in response to the external magnetic field and having a second magnetic field saturation characteristic. The first magnetic field saturation characteristic is different from the second magnetic field saturation characteristic. The sensor is configured to use the secondary signal to correct for errors in the output signal arising from saturation of the primary transducer.
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公开(公告)号：US20220236119A1
公开(公告)日：2022-07-28
申请号：US17159956
申请日：2021-01-27
Applicant: NXP B.V.
Inventor： Robert van Veldhoven , Sha Xia
Abstract: An integrated circuit (IC) chip includes a first temperature sensor of a first type and a second temperature sensor of a second type that differs from the first type. A method implemented in the IC chip entails calibrating the second temperature sensor utilizing the first temperature sensor and following the calibrating operation, sensing a temperature of the IC chip utilizing the second temperature sensor. The first temperature sensor may be a bipolar junction transistor-based temperature sensor configured to undergo a voltage calibration. Alternatively, the first temperature sensor may be a thermal-diffusivity-based temperature sensor. The second temperature sensor may be a low power consumption sensor relative to the first temperature sensor, and the first temperature sensor may be powered off following calibration of the second temperature sensor.
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公开(公告)号：US20220019883A1
公开(公告)日：2022-01-20
申请号：US16933568
申请日：2020-07-20
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which may utilize a reference ADC or a digital training signal representing a reference ADC that has less distortion errors than the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.
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公开(公告)号：US11101810B1
公开(公告)日：2021-08-24
申请号：US16933617
申请日：2020-07-20
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which utilizes a filtered output of the analog-to-digital converter that has less distortion errors than the unfiltered output of the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.
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5.发明公开公开(公告)号：US20240267056A1
公开(公告)日：2024-08-08
申请号：US18106803
申请日：2023-02-07
Applicant: NXP B.V.
Inventor： Erik Olieman , Alphons Litjes , Robert van Veldhoven
CPC classification number: H03M1/124 , H03M1/0626 , H03M1/08
Abstract: A system and method of analog to digital conversion including an adjustable ADC, FIR filter circuitry, and a noise setting controller. The ADC samples an analog input signal to provide digital samples at a sample rate that is Y times an output rate of output digital values. The FIR filter circuitry includes Y taps with Y corresponding coefficients and is configured to filter the digital samples from the ADC and to provide filtered digital samples at the sample rate. decimation circuitry may be included to decimate the filtered digital samples by Y to provide the output digital values. The noise setting controller provides an adjustment value to the ADC to adjust noise contribution of the digital samples provided by the ADC based on corresponding coefficients of the FIR filter circuitry. The ADC is adjusted to reduce noise contribution of digital samples that correspond with higher FIR filter coefficients.
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Patent Agency Ranking
公开(公告)号：US20240030934A1
公开(公告)日：2024-01-25
申请号：US18052425
申请日：2022-11-03
Applicant: NXP B.V.
Inventor： Victor Pecanins Martinez , Robert van Veldhoven
IPC: H03M3/00
Abstract: A continuous-time delta-sigma modulator, CTDSM (400, 500, 700, 800) is described that comprises: an operational transconductance amplifier, OTA, (406, 506, 706, 806) having an input port (404, 504, 719, 739, 819, 839) configured to receive an analog input signal and an output port (408, 508, 707, 708, 807, 808); an input low pass filter network comprising at least one input resistor, R1, (402, 502, 702, 722, 802, 822) at least one first shunt capacitor, C1, (403, 503, 703, 803) and at least one feedback resistor, Rdac (410, 510, 710, 810, 730, 830) connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, (415, 515, 715, 815) in parallel to a second shunt capacitor, C2, (414, 514, 714, 814), and coupled to the output port (408, 508, 707, 708, 807, 808) of the OTA; a quantizer (413, 513, 713, 813) connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein the input and output port of the OTA connected by a third feedforward-feedback capacitor, C3, (409, 509, 709, 729, 809, 829) arranged to provide a positive feedback around the OTA.
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公开(公告)号：US20230118374A1
公开(公告)日：2023-04-20
申请号：US17501757
申请日：2021-10-14
Applicant: NXP B.V.
Inventor： Robert van Veldhoven , John Pigott
IPC: H03F3/387
Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.
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公开(公告)号：US11502698B1
公开(公告)日：2022-11-15
申请号：US17398391
申请日：2021-08-10
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
IPC: H03M3/00
Abstract: A passive sigma-delta modulator including first modulator loop, a second modulator loop, and a digital combiner providing an output signal. The first modulator loop includes a first quantizer, a first passive summing junction, a first continuous-time passive analog loop filter, and a first feedback path. The second modulator loop includes a second quantizer, analog transfer circuitry, a second continuous-time passive summing junction, a second passive analog loop filter, a second feedback path, and digital transfer circuitry having a gain that is substantially a reciprocal of the analog transfer circuitry. A digital noise cancelation filter may be located between the first quantizer and the digital combiner, or an analog noise cancelation filter may be provided within the second modulator loop. Single-ended or differential configurations are contemplated.
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公开(公告)号：US20170154949A1
公开(公告)日：2017-06-01
申请号：US15352770
申请日：2016-11-16
Applicant: NXP B.V.
Inventor： Robert van Veldhoven , Ibrahim Candan , Johannes van Geloven
CPC classification number: H01L28/20 , G05F1/561 , H01L27/0802 , H01L28/00 , H01L29/8605
Abstract: A diffused resistor and method for forming a diffused resistor are provided. The diffused resistor comprises a substrate having a first conductivity type; a first well within the substrate having a second conductivity type; and a second well within the first well having the first conductivity type. The resistor further comprises a first and second contact for coupling the resistor to further circuitry. The first and second contacts are each coupled to both the first well and the second well.
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公开(公告)号：US20240396565A1
公开(公告)日：2024-11-28
申请号：US18201085
申请日：2023-05-23
Applicant: NXP B.V.
Inventor： Maarten Jelmar MOLENDIJK , Robert van Veldhoven
Abstract: A system includes a time-interleaved analog-to-digital converter (TI ADC). The TI ADC includes a plurality of ADC units connected in parallel between an input terminal and an output terminal of the time-interleaved ADC. An ADC tag generator is configured to output a first identifier of a first ADC unit of the plurality of ADC when the first ADC unit is enabled. An error correction system is configured to receive a first digital signal from the output terminal of the time-interleaved ADC, receive the first identifier of the first ADC unit from the ADC tag generator, modify the first digital signal to generate a first corrected digital signal by compensating for first analog-to-digital conversion errors occurring within the first ADC unit by applying a first error correction scheme that is associated with the first ADC unit, and output the first corrected digital signal.
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