公开(公告)号：US20240380368A1

公开(公告)日：2024-11-14

申请号：US18783826

申请日：2024-07-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshifumi TAKAHASHI

IPC: H03F1/52 ,  H03F3/24

Abstract: There is provided a limiter circuit and a power amplifier circuit that are capable of effectively limiting output power of an amplifying transistor based on the amplitude of an input signal. A limiter circuit is connectable to an amplifying transistor that amplifies and outputs a radio frequency signal and controls a voltage to be applied to the amplifying transistor, based on the radio frequency signal. The limiter circuit includes an input signal detection transistor that detects power of the radio frequency signal and a voltage limiting transistor that limits the voltage to be applied to the amplifying transistor, based on current flowing to the input signal detection transistor.

公开(公告)号：US20210344312A1

公开(公告)日：2021-11-04

申请号：US17242815

申请日：2021-04-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tsutomu KOBORI ,  Shingo YANAGIHARA ,  Yoshifumi TAKAHASHI ,  Hiroshi OKABE

IPC: H03F3/24 ,  H03F3/195 ,  H01L23/31

Abstract: A power amplifier device includes a semiconductor substrate; a plurality of first transistors that are provided on the semiconductor substrate and receive input of a radio-frequency signal; a plurality of second transistors that are provided on the semiconductor substrate and electrically connected to the respective plurality of first transistors, and output a radio-frequency output signal obtained by amplifying the radio-frequency signal; a plurality of first bumps provided so as to overlay the respective plurality of first transistors; and a second bump provided away from the plurality of first bumps and provided so as not to overlay the plurality of first transistors and the plurality of second transistors. When viewed in plan from a direction perpendicular to a surface of the semiconductor substrate, a first transistor and a first bump, a second transistor, the second bump, a second transistor, and a first transistor and a first bump are arranged in sequence.

公开(公告)号：US20210058043A1

公开(公告)日：2021-02-25

申请号：US16998598

申请日：2020-08-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshifumi TAKAHASHI

IPC: H03F3/24 ,  H03F3/195

Abstract: A power amplifier circuit includes an amplifier unit disposed on a die of a semiconductor device. The amplifier unit includes an amplifier transistor. The power amplifier circuit further includes a detector transistor disposed on the die of the semiconductor device, a variable attenuator that compensates for a gain of the amplifier unit, a bias level setting holding unit that holds a bias level setting value, which is set based on at least a detection value of the detector transistor, and a bias generation unit that generates a bias value of the variable attenuator based on the bias level setting value.

公开(公告)号：US20210013164A1

公开(公告)日：2021-01-14

申请号：US16925006

申请日：2020-07-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tsutomu KOBORI ,  Hiroshi OKABE ,  Shigeru YOSHIDA ,  Shingo YANAGIHARA ,  Yoshifumi TAKAHASHI

IPC: H01L23/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/737

Abstract: A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged.