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公开(公告)号：US20220238276A1
公开(公告)日：2022-07-28
申请号：US17571576
申请日：2022-01-10
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazuhisa UCHIDA
Abstract: A multilayer ceramic capacitor includes a multilayer body including the dielectric ceramic layers and the internal electrode layers which are laminated, and external electrodes connected to the internal electrode layers. The multilayer body includes segregation including Si as a main component in a vicinity of an end of the internal electrode layer in a width direction. An average particle size of the dielectric particles in the vicinity of the end of the internal electrode layer in the width direction in the dielectric ceramic layer is smaller than an average particle size of a dielectric particles in a central portion of the internal electrode layer in the width direction in the dielectric ceramic layer.
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公开(公告)号：US20230019604A1
公开(公告)日：2023-01-19
申请号：US17849759
申请日：2022-06-27
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazuhisa UCHIDA , Yukie WATANABE
Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric ceramic layers and internal electrode layers laminated alternately in a lamination direction, and a pair of external electrodes on both end portions in the length direction of the multilayer body and respectively connected to the internal electrode layers. The pair of external electrodes each include a base region covering at least each of the first and second end surfaces, connected to the internal electrode layers, and including Cu as a main component, a cover region on the base region to cover the base region, and including Ag as a main component, and a reaction region between the base region and the cover region including Cu included in the base region and Ag included in the cover region reacting with each other.
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公开(公告)号：US20230386744A1
公开(公告)日：2023-11-30
申请号：US18233407
申请日：2023-08-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazuhisa UCHIDA
CPC classification number: H01G4/1227 , H01G4/012 , H01G4/30 , H01G4/2325
Abstract: A multilayer ceramic capacitor includes a multilayer body including the dielectric ceramic layers and the internal electrode layers which are laminated, and external electrodes connected to the internal electrode layers. The multilayer body includes segregation including Si as a main component in a vicinity of an end of the internal electrode layer in a width direction. An average particle size of the dielectric particles in the vicinity of the end of the internal electrode layer in the width direction in the dielectric ceramic layer is smaller than an average particle size of a dielectric particles in a central portion of the internal electrode layer in the width direction in the dielectric ceramic layer.
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公开(公告)号：US20230317374A1
公开(公告)日：2023-10-05
申请号：US18109309
申请日：2023-02-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Natsuko OKUBO , Akito MORI , Kazuhisa UCHIDA
CPC classification number: H01G4/1227 , H01G4/008 , H01G4/012 , H01G4/30 , H01G4/1236
Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers, and external electrodes. The multilayer body includes side margin portions made of a dielectric. In the internal electrode layers, a width of an extension electrode portion is smaller than a width of a counter electrode portion. The side margin portions each include Ba and Ti as a main component and Mg as a sub component. The Mg content is about 0.2 mol% or more and about 2.0 mol% or less with respect to 100 mol of Ti. The internal electrode layers each include Ni as a main component, and an end portion of the counter electrode portion includes Mg as a sub component. The Mg content is about 0.13 mol% or more and about 0.39 mol% or less with respect to 100 mol of Ni.
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公开(公告)号：US20200312555A1
公开(公告)日：2020-10-01
申请号：US16822068
申请日：2020-03-18
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Akitaka DOI , Akito MORI , Kazuhisa UCHIDA
Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second electrode layers laminated in a lamination direction, and first and second external electrodes respectively connected to the first and second internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The first and second internal electrode layers and the first and second external electrodes include Ni. In a cross section including the lamination direction and a width direction, a Ni content of the peripheral layer portion is larger at a surface portion than at a central portion in a thickness direction, and a Ni content of the side margin is larger at a surface portion than at a central portion in a thickness direction of the side margin.
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Patent Agency Ranking
公开(公告)号：US20220102076A1
公开(公告)日：2022-03-31
申请号：US17411147
申请日：2021-08-25
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shinya ISOTA , Takehisa SASABAYASHI , Kazuhisa UCHIDA , Hideyuki HASHIMOTO , Yuta OSHIMA
Abstract: A multilayer ceramic capacitor includes a base body including first and second main surfaces, first and second side surfaces, first and second end surfaces, and dielectric layers and internal electrode layers, and external electrodes at the first and second end surfaces, and electrically connected to the internal electrode layers. The base body includes an inner layer, first and second outer layers, first and second side margin portions. The dielectric layers in the inner layer and the first and second outer layers include main crystal grains including barium and titanium, and with respect to 100 parts by mol of titanium, nickel in an amount of about 0.2 to about 3.0 parts by mol, and at least one rare earth element selected from yttrium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium in an amount of about 0.6 parts to about 2.0 parts by mol.
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公开(公告)号：US20150187498A1
公开(公告)日：2015-07-02
申请号：US14541212
申请日：2014-11-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazuhisa UCHIDA , Yoshito SAITO , Jun IKEDA
CPC classification number: H01G4/1227 , H01G4/012 , H01G4/1218 , H01G4/30
Abstract: In a multilayer ceramic capacitor, an inner ceramic layer includes a perovskite-type compound containing Ba and Ti. A region within an electrically effective portion of the inner ceramic layers sandwiched between inner electrodes, which is near an area where inner and outer electrodes connect to each other, is subjected to a mapping analysis using EDS. ((L2−L3)/L1)×100≧50 is satisfied, L1 denotes a total length of ceramic grain boundaries detected from a TEM transmission image, L2 denotes a total length of grain boundaries, detected from a mapping image and the TEM transmission image, where the rare earth element is present, and L3 denotes a total length of portions, detected from a mapping image and the TEM transmission image, in which the grain boundaries where the rare earth element is present and grain boundaries where at least one of Mn, Mg, and Si is present are overlapped.
Abstract translation: 在多层陶瓷电容器中，内部陶瓷层包括含有Ba和Ti的钙钛矿型化合物。 夹在内部电极之间的内部陶瓷层的电学有效部分内的区域，其内部和外部电极彼此连接的区域附近，使用EDS进行映射分析。 （（L2-L3）/ L1）×100≥50，L1表示从TEM透射图像检测出的陶瓷晶界的总长度，L2表示从映射图像和TEM透射检测出的晶界的总长度 图像，其中存在稀土元素，L3表示从映射图像和TEM透射图像检测的部分的总长度，其中存在稀土元素的晶界和晶界，其中至少一个 Mn，Mg和Si存在重叠。
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公开(公告)号：US20150187497A1
公开(公告)日：2015-07-02
申请号：US14582260
申请日：2014-12-24
Applicant: MURATA MANUFACTURING CO., LTD.
Inventor： Yoshito SAITO , Jun IKEDA , Kazuhisa UCHIDA
CPC classification number: H01G4/1218 , G01N23/2252 , H01G4/0085 , H01G4/1227 , H01G4/2325 , H01G4/30
Abstract: In a monolithic ceramic capacitor, ceramic layers defining inner layers are mainly composed of a perovskite compound containing Ba and Ti. A portion of an electrically effective section in the ceramic layers near a connecting portion between the inner electrodes and an outer electrode undergoes mapping analysis by an energy-dispersive method. In regions of the resulting mapping image, the regions extending from the interfaces between the inner electrodes and a corresponding one of the ceramic layers to positions about ⅓ of the thickness of the ceramic layer in the stacking direction, ((L2−L3)/L1)×100≧50 is satisfied, where L1 represents the total length of grain boundaries, L2 represents the total length of grain boundaries where a rare-earth element is present, and L3 represents the total length of portions where the grain boundaries where the rare-earth element is present are overlapped with grain boundaries with a specific element present.
Abstract translation: 在单片陶瓷电容器中，限定内层的陶瓷层主要由含有Ba和Ti的钙钛矿化合物组成。 陶瓷层中靠近内部电极和外部电极之间的连接部分的电气部分的一部分通过能量分散方法进行映射分析。 在所得到的映射图像的区域中，从内部电极和对应的一个陶瓷层之间的界面延伸到层叠方向上约为陶瓷层厚度的1/3的区域（（L2-L3）/ L1 ）×100≥50，其中L1表示晶界的总长度，L2表示存在稀土元素的晶界的总长度，L3表示稀土元素的晶界的部分的总长度 存在的地层元素与存在特定元素的晶界重叠。
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公开(公告)号：US20240395460A1
公开(公告)日：2024-11-28
申请号：US18797722
申请日：2024-08-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yoshiyuki ABE , Kazuhisa UCHIDA
Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
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公开(公告)号：US20230395324A1
公开(公告)日：2023-12-07
申请号：US18237505
申请日：2023-08-24
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yoshiyuki ABE , Kazuhisa UCHIDA
CPC classification number: H01G4/1227 , H01G4/0085 , H01G4/2325 , H01G4/30
Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
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