公开(公告)号：US20240395460A1

公开(公告)日：2024-11-28

申请号：US18797722

申请日：2024-08-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshiyuki ABE ,  Kazuhisa UCHIDA

IPC: H01G4/12 ,  H01G4/008 ,  H01G4/232 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.

公开(公告)号：US20240387105A1

公开(公告)日：2024-11-21

申请号：US18789816

申请日：2024-07-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Motonori TAKEDA ,  Yoshiyuki ABE

IPC: H01G2/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: An electronic component includes a component body with a length in a length direction, and first and second external electrodes respectively provided at both ends of the component body in the length direction. The component body includes a central outer peripheral portion protruding outwardly beyond the first and second external electrodes in one direction orthogonal or substantially orthogonal to the length direction, in at least a portion of an area exposed between the pair of external electrodes.

公开(公告)号：US20230395324A1

公开(公告)日：2023-12-07

申请号：US18237505

申请日：2023-08-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshiyuki ABE ,  Kazuhisa UCHIDA

IPC: H01G4/12 ,  H01G4/008 ,  H01G4/232 ,  H01G4/30

CPC classification number: H01G4/1227 ,  H01G4/0085 ,  H01G4/2325 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.

公开(公告)号：US20220270820A1

公开(公告)日：2022-08-25

申请号：US17668411

申请日：2022-02-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshiyuki ABE

IPC: H01G2/00 ,  H01G4/30 ,  H01G4/248 ,  H01G4/232

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, first and second main surfaces opposing each other in a lamination direction, first and second end surfaces opposing each other in a length direction which intersects the lamination direction, and first and second side surfaces opposing each other in a width direction which intersects the lamination direction and the length direction, and external electrodes on the first and second end surfaces, and each electrically connected to the internal electrode layers, wherein the multilayer body includes a slit in at least one of the first side surface, the second side surface, and the second main surface defining and functioning as a board-mounting surface.

公开(公告)号：US20220262568A1

公开(公告)日：2022-08-18

申请号：US17591628

申请日：2022-02-03

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshiyuki ABE ,  Kazuhisa UCHIDA

IPC: H01G4/12 ,  H01G4/30 ,  H01G4/232 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.