公开(公告)号：US06953925B2

公开(公告)日：2005-10-11

申请号：US10424482

申请日：2003-04-28

申请人： Ming Fang ,  Fuchao Wang ,  Hai Ding

发明人： Ming Fang ,  Fuchao Wang ,  Hai Ding

IPC分类号： G02B3/00 ,  G02B27/10 ,  H01L27/00 ,  H01L27/14 ,  H01L27/146 ,  H01L31/00 ,  H01L31/0216 ,  H01L31/0232 ,  H01L31/062 ,  H01L31/10 ,  H01L31/113

CPC分类号： H01L27/14685 ,  H01L27/14601 ,  H01L27/14627 ,  H01L31/02327

摘要： A microlens of an inorganic material having a relatively high index of refraction is formed with a convex lower surface for refracting light from above through an underlying spacer layer to converge on a photodiode therebelow. The microlens and photodiode may be replicated in an array of such elements along with color filters and CMOS circuit elements on a semiconductor chip to provide an image sensor. The spacer layer, which has a relatively low refractive index, is subjected to a selective isotropic etch through an opening in an etch mask to define a concave surface that forms an interface with the convex lower surface of the microlens upon subsequent conformal deposition of the material of the microlens.

摘要翻译： 具有较高折射率的无机材料的微透镜形成有用于通过下面的间隔层从上方折射光以会聚在其下的光电二极管上的凸下表面。 微透镜和光电二极管可以与半导体芯片上的滤色器和CMOS电路元件一起复制在这样的元件的阵列中，以提供图像传感器。 具有相对较低折射率的间隔层通过蚀刻掩模中的开口进行选择性各向同性蚀刻，以限定在随后的材料共形沉积时与微透镜的凸下表面形成界面的凹面 的微透镜。

公开(公告)号：US09059174B2

公开(公告)日：2015-06-16

申请号：US12265595

申请日：2008-11-05

申请人： Hai Ding ,  Fuchao Wang ,  Zhiyong Xie

发明人： Hai Ding ,  Fuchao Wang ,  Zhiyong Xie

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L27/108

CPC分类号： H01L23/5256 ,  H01L21/76892 ,  H01L23/5258 ,  H01L27/10894 ,  H01L2924/0002 ,  Y02E60/12 ,  H01L2924/00

摘要： Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.

摘要翻译： 提供制造多层半导体结构的方法。 在一个实施例中，一种方法包括在半导体结构上沉积第一介电层，在第一介电层上沉积第一金属层，图案化第一金属层以形成多个第一金属线，以及在第 第一金属线和第一介电层。 该方法还包括在所选择的第一金属线上去除第二电介质层的一部分以暴露每个所选择的第一金属线的相应顶表面。 该方法还包括将所选择的第一金属线的厚度减小到小于未选择的第一金属线的厚度。 还提供了多层半导体结构。

公开(公告)号：US20100109122A1

公开(公告)日：2010-05-06

申请号：US12265595

申请日：2008-11-05

申请人： Hai Ding ,  Fuchao Wang ,  Zhiyong Xie

发明人： Hai Ding ,  Fuchao Wang ,  Zhiyong Xie

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/76892 ,  H01L23/5258 ,  H01L27/10894 ,  H01L2924/0002 ,  Y02E60/12 ,  H01L2924/00

摘要： Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.

摘要翻译： 提供制造多层半导体结构的方法。 在一个实施例中，一种方法包括在半导体结构上沉积第一介电层，在第一介电层上沉积第一金属层，图案化第一金属层以形成多个第一金属线，以及在第 第一金属线和第一介电层。 该方法还包括在所选择的第一金属线上去除第二电介质层的一部分以暴露每个所选择的第一金属线的相应顶表面。 该方法还包括将所选择的第一金属线的厚度减小到小于未选择的第一金属线的厚度。 还提供了多层半导体结构。

公开(公告)号：US08110117B2

公开(公告)日：2012-02-07

申请号：US12422732

申请日：2009-04-13

申请人： Fuchao Wang ,  Ming Fang

发明人： Fuchao Wang ,  Ming Fang

IPC分类号： B44C1/22

CPC分类号： B41J2/1601 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B41J2202/13 ,  B41J2202/16

摘要： A method includes forming a recess in a first surface of a substrate, the recess having a width, depth, and height selected to correspond to a width, depth, and height of a fluid chamber, forming a sacrificial material in the recess, forming a first heater element, forming a metal layer overlying the first heater element, and forming a nozzle opening in the metal layer to expose the sacrificial material. The method also includes forming a path from a second surface of the substrate to expose the sacrificial material and removing the sacrificial material from the recess to expose the chamber with the selected width, depth, and height, the chamber in fluid communication with the path, the nozzle opening, and a surrounding environment.

摘要翻译： 一种方法包括在基板的第一表面中形成凹槽，所述凹槽具有选定为对应于流体室的宽度，深度和高度的宽度，深度和高度，在凹槽中形成牺牲材料，形成凹陷 第一加热器元件，形成覆盖在第一加热器元件上的金属层，以及在金属层中形成喷嘴开口以露出牺牲材料。 该方法还包括从衬底的第二表面形成路径以暴露牺牲材料并从凹部移除牺牲材料，以使选定的宽度，深度和高度暴露腔室，该腔室与路径流体连通， 喷嘴开口和周围环境。

公开(公告)号：US20070200172A1

公开(公告)日：2007-08-30

申请号：US11355937

申请日：2006-02-16

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： H01L27/12

CPC分类号： H01L29/78624 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/7824

摘要： A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N− regions), and the second doped region could represent a p-type region (such as a P− region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.

摘要翻译： 薄膜功率晶体管包括在衬底上的多个第一掺杂区域和形成主体的第二掺杂区域。 身体的至少一部分设置在多个第一掺杂区域之间。 薄膜功率晶体管还包括在衬底上的栅极。 薄膜功率晶体管还包括介电层，其至少一部分设置在（i）栅极和（ii）第一和第二掺杂区域之间。 此外，薄膜功率晶体管包括接触多个第一掺杂区域的多个触点，其中多个第一掺杂区域形成薄膜功率晶体管的源极和漏极。 第一掺杂区域可以表示n型区域（例如N区域），并且第二掺杂区域可以表示p型区域（例如P-区域）。 第一掺杂区域也可以表示p型区域，第二掺杂区域可以表示n型区域。

公开(公告)号：US07881594B2

公开(公告)日：2011-02-01

申请号：US12005862

申请日：2007-12-27

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： F24H1/10

CPC分类号： B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

摘要： An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

摘要翻译： 集成半导体加热组件包括半导体衬底，形成在其中的腔室以及与腔室流体连通的出口，允许流体响应于加热室而离开腔室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。

公开(公告)号：US20080206919A1

公开(公告)日：2008-08-28

申请号：US12111061

申请日：2008-04-28

申请人： Fuchao Wang ,  Ming Fang

发明人： Fuchao Wang ,  Ming Fang

IPC分类号： H01L21/00

CPC分类号： H01L33/20 ,  G02B3/00 ,  H01L31/02327 ,  H01L33/58

摘要： A semiconductor device includes a semiconductor material substrate, an opto-electric component formed on the substrate, and a first transparent layer formed on an upper surface of the substrate over the component, the layer having a planar upper surface with a cavity formed therein. The first transparent layer has a selected thickness and a first index of refraction. The semiconductor device further includes a lens having a second index of refraction, the lens being formed in the cavity by flowing a flowable dielectric over the substrate. An upper surface of the lens and the upper surface of the transparent layer may be coplanar, or alternatively, they may lie in separate planes. The semiconductor device may also include a second transparent layer formed over the first layer and lens, as a passivation layer.

摘要翻译： 半导体器件包括半导体材料基板，形成在基板上的光电部件和形成在该部件上的基板的上表面上的第一透明层，该层具有形成在其中的空腔的平面上表面。 第一透明层具有选定的厚度和第一折射率。 半导体器件还包括具有第二折射率的透镜，透镜通过使可流动电介质流过衬底而形成在空腔中。 透镜的上表面和透明层的上表面可以是共面的，或者可以位于分开的平面中。 半导体器件还可以包括形成在第一层和透镜上的第二透明层作为钝化层。

公开(公告)号：US06586320B2

公开(公告)日：2003-07-01

申请号：US10053109

申请日：2001-11-02

申请人： Fuchao Wang ,  Ming Fang

发明人： Fuchao Wang ,  Ming Fang

IPC分类号： H01L213205

CPC分类号： H01L21/28518 ,  H01L21/28061 ,  H01L29/4933 ,  H01L29/7833

摘要： A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

公开(公告)号：US06350684B1

公开(公告)日：2002-02-26

申请号：US09594868

申请日：2000-06-15

申请人： Fuchao Wang ,  Ming Fang

发明人： Fuchao Wang ,  Ming Fang

IPC分类号： H01L2144

CPC分类号： H01L21/28061 ,  H01L29/4933

摘要： A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner suicides with less likelihood of delamination or metal oxidation may thus be formed.

摘要翻译： 在集成电路内采用具有调整到硅化物和相邻层之间的界面处的表面状态的可变内部金属浓度的硅化物。 在靠近相邻层的界面附近使用更高的硅/金属（富硅）比例，以减少与下面的多晶硅或上覆氧化物的晶格失配，从而减少应力和分层的可能性。 在硅化物的内部区域内采用较低的硅/金属比，降低了电阻率。 可变硅/金属比例通过在硅化物沉积期间控制反应气体浓度或流速来实现。 因此可能形成较少的分层或金属氧化的可能性的较小的自杀。

公开(公告)号：US20110081138A1

公开(公告)日：2011-04-07

申请号：US12968150

申请日：2010-12-14

申请人： Ming Fang ,  Fuchao Wang

发明人： Ming Fang ,  Fuchao Wang

IPC分类号： H05B3/82 ,  B23P19/04

CPC分类号： B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

摘要： An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

摘要翻译： 集成半导体加热组件包括半导体衬底，形成在其中的腔室以及与腔室流体连通的出口，允许流体响应于加热室而离开腔室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。