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公开(公告)号:US12027195B2
公开(公告)日:2024-07-02
申请号:US17863196
申请日:2022-07-12
发明人: Qi Dong , Xuesong Li
IPC分类号: G11C11/40 , G11C11/4072 , G11C11/4074 , G11C11/4096
CPC分类号: G11C11/4072 , G11C11/4074 , G11C11/4096
摘要: Methods, apparatuses, and non-transitory machine-readable media associated with a memory device training are described. An apparatus for memory device training can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to perform a plurality of training rounds associated with performance of the memory device at different temperatures and different voltages and write results of the plurality of training rounds to a plurality of mode registers of the memory device. The processing device can also be configured to log an initial group identifier into a current GID MR as a reference identifier and in response to a threshold deviation from the reference ID or in response to lack of deviation outside the threshold for a threshold amount of time, retrieve an updated training setting from the results in the plurality of mode registers and enable the updated training setting.
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公开(公告)号:US12019892B2
公开(公告)日:2024-06-25
申请号:US17842197
申请日:2022-06-16
IPC分类号: G06F3/06
CPC分类号: G06F3/0644 , G06F3/0604 , G06F3/0643 , G06F3/0673
摘要: Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.
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公开(公告)号:US20240126449A1
公开(公告)日:2024-04-18
申请号:US17967339
申请日:2022-10-17
发明人: Qi Dong
IPC分类号: G06F3/06
CPC分类号: G06F3/0619 , G06F3/0634 , G06F3/0656 , G06F3/0673
摘要: Apparatuses, systems, and methods for buffer threshold monitoring to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include buffering data in a first memory device, writing the buffered data from the first memory device to a second memory device, determining that the first memory device is storing at least a threshold amount of data, and sending a first signal to the second memory device in response to determining that the first memory device is storing at least the threshold amount of data, wherein the first signal causes the second memory device to enter an increased write performance mode.
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公开(公告)号:US20230266880A1
公开(公告)日:2023-08-24
申请号:US17652050
申请日:2022-02-22
发明人: Qi Dong , Poorna Kale
IPC分类号: G06F3/06
CPC分类号: G06F3/0611 , G06F3/0659 , G06F3/0679
摘要: Methods, systems, and devices for techniques to improve latency for gaming applications are described. The memory system may be configured to operate in a gaming mode that may enable faster load times. In some cases, the gaming mode may enable faster game download from an external server. In some cases, the gaming mode may enable faster transferring of files between volatile storage and non-volatile storage at the memory system. The gaming mode may enable faster read and write operations, and faster switching between one or more gaming applications. The memory system may additionally or alternatively be configured to operate in a non-gaming mode which may improve reliability and retention for other, non-gaming applications. The memory system may switch between the two modes depending on an application being executed by the system.
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公开(公告)号:US11977737B2
公开(公告)日:2024-05-07
申请号:US17652050
申请日:2022-02-22
发明人: Qi Dong , Poorna Kale
IPC分类号: G06F3/06
CPC分类号: G06F3/0611 , G06F3/0659 , G06F3/0679
摘要: Methods, systems, and devices for techniques to improve latency for gaming applications are described. The memory system may be configured to operate in a gaming mode that may enable faster load times. In some cases, the gaming mode may enable faster game download from an external server. In some cases, the gaming mode may enable faster transferring of files between volatile storage and non-volatile storage at the memory system. The gaming mode may enable faster read and write operations, and faster switching between one or more gaming applications. The memory system may additionally or alternatively be configured to operate in a non-gaming mode which may improve reliability and retention for other, non-gaming applications. The memory system may switch between the two modes depending on an application being executed by the system.
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公开(公告)号:US11961547B2
公开(公告)日:2024-04-16
申请号:US17668197
申请日:2022-02-09
发明人: Qi Dong , Poorna Kale
IPC分类号: G11C7/00 , G06F11/07 , G11C11/406
CPC分类号: G11C11/40611 , G06F11/076 , G06F11/0772 , G11C11/40622 , G11C2211/4061
摘要: Methods, systems, and devices for techniques for memory system refresh are described. In some cases, a memory system may prioritize refreshing blocks of memory cells containing control information for the file system of the memory system. For example, the memory system may identify a block of memory cells containing control information and adjust an error threshold for refreshing the blocks of memory cells to be lower than an error threshold for refreshing the blocks of memory cells containing data other than control information. Additionally or alternatively, the memory system may perform a refresh control operation for the block of memory cells with a higher frequency (e.g., more frequently) than for other blocks of memory cells.
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公开(公告)号:US20240112515A1
公开(公告)日:2024-04-04
申请号:US17936601
申请日:2022-09-29
发明人: Qi Dong
IPC分类号: G07C9/28 , G06F9/4401 , G06F9/54
CPC分类号: G07C9/28 , G06F9/4406 , G06F9/545
摘要: Exemplary methods, apparatuses, and systems include an intelligent boot manager for controlling initialization of components of vehicle computing systems. The intelligent boot manager receives an access request for a vehicle. The intelligent boot manager initializes a set of components of vehicle systems of the vehicle in response to the access request. The intelligent boot manager executes a first portion of code from a read-only memory (ROM) location, the first portion of code configuring a processor to initialize a random-access memory (RAM) location. The intelligent boot manager downloads a set of applications to the RAM location. The intelligent boot manager receives an engine start request for the vehicle, wherein the engine start request is distinct from the access request. The intelligent boot manager initiates an engine start sequence of the vehicle in response to the engine start request.
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公开(公告)号:US20230393757A1
公开(公告)日:2023-12-07
申请号:US17889810
申请日:2022-08-17
发明人: Qi Dong
IPC分类号: G06F3/06
CPC分类号: G06F3/0619 , G06F3/0632 , G06F3/0683
摘要: The present disclosure includes apparatuses, methods, and systems for storing non-volatile memory initialization failures. In an example, a method can include initializing a volatile memory die, initializing a first non-volatile memory die in response to initializing the volatile memory die, copying executable instructions from the first non-volatile memory die to the volatile memory die in response to initializing the first non-volatile memory die, initializing the second non-volatile memory die in response to initializing the first non-volatile memory die, and storing a failure record in the first non-volatile memory die in response to an error occurring during the initialization of the second non-volatile memory die.
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公开(公告)号:US20230061879A1
公开(公告)日:2023-03-02
申请号:US17463408
申请日:2021-08-31
发明人: Poorna Kale , Christopher Joseph Bueb , Te-Chang Lin , Qi Dong
IPC分类号: H04N5/77 , H04N5/91 , H04N7/18 , G06F12/1009
摘要: A memory system having multiple address tables to translate logical addresses to physical addresses at different granularity levels. For example, a first address table is associated with a first block size of translating logical addresses for accessing system files and application files; and a second address table is associated with a second block size of translating logical addresses for storing and/or retrieving data from an image sensor of a surveillance camera. A user interface can be used to access a configuration option to specify the second block size; and a user may indicate a typical size of an image or video file to be recorded by the surveillance camera to calculate the second block size and thus configured the second address table for a partition to record the image or video files.
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公开(公告)号:US11711488B2
公开(公告)日:2023-07-25
申请号:US17463408
申请日:2021-08-31
发明人: Poorna Kale , Christopher Joseph Bueb , Te-Chang Lin , Qi Dong
IPC分类号: H04N5/77 , G06F12/1009 , H04N5/91 , H04N7/18 , G06F3/0484
CPC分类号: H04N5/77 , G06F12/1009 , H04N5/91 , H04N7/183 , G06F3/0484 , G06F2212/657
摘要: A memory system having multiple address tables to translate logical addresses to physical addresses at different granularity levels is disclosed. For example, a first address table is associated with a first block size of translating logical addresses for accessing system files and application files; and a second address table is associated with a second block size of translating logical addresses for storing and/or retrieving data from an image sensor of a surveillance camera. A user interface can be used to access a configuration option to specify the second block size; and a user may indicate a typical size of an image or video file to be recorded by the surveillance camera to calculate the second block size and thus configure the second address table for a partition to record the image or video files.
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