公开(公告)号：US20240220273A1

公开(公告)日：2024-07-04

申请号：US18527004

申请日：2023-12-01

Applicant: Meta Platforms Technologies, LLC

Inventor： Vignesh Vivekraja ,  Tomonari Tohara ,  Reza Tusi ,  Abuduwaili Tuoheti ,  Javid Jaffari ,  Vlad Fruchter ,  David Vakrat ,  Ohad Meitav

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3893 ,  G06F9/3001 ,  G06F9/3012

Abstract: In one embodiment, a system comprising a processor and a non-transitory memory coupled to the processor comprising instructions executable by the processor. The processor, comprising an internal memory; a Multiply-Accumulate (MAC) array; a first vector register array; a second vector register array; and a third vector register array, is operable when executing a first instruction among the instructions to feed a weight vector array from the second vector register array to the MAC array, broadcast an input activation vector to the MAC array, multiply an input activation value broadcast to the MAC unit from the input activation vector and a weight value fed to the MAC unit from the weight vector array at each MAC unit in the MAC array, and store a partial output activation vector to the third vector register array, wherein the partial output activation vector is the output of the MAC array.

公开(公告)号：US11580026B2

公开(公告)日：2023-02-14

申请号：US17578392

申请日：2022-01-18

Applicant: META PLATFORMS TECHNOLOGIES, LLC

Inventor： Vlad Fruchter ,  Richard Lawrence Greene ,  Hideo Tamama

IPC: G06F12/0871 ,  G06F3/06 ,  G06F12/02 ,  G06F12/14

Abstract: In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The first control unit may be configured to obtain, from the second control unit, a first memory address associated with a data reading process of the second processing unit, receive a write request from the first processing unit, the read request having an associated second memory address, and write data into the memory region based on the write request in response to a determination that the second memory address falls outside of the guarded reading region.

公开(公告)号：US11481323B2

公开(公告)日：2022-10-25

申请号：US16582403

申请日：2019-09-25

Applicant: Meta Platforms Technologies, LLC

Inventor： Vlad Fruchter ,  Richard Lawrence Greene ,  Hideo Tamama

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16 ,  G06F9/50 ,  G06F12/0802 ,  G06F12/14

Abstract: In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.

公开(公告)号：US12093101B2

公开(公告)日：2024-09-17

申请号：US17682917

申请日：2022-02-28

Applicant: Meta Platforms Technologies, LLC

Inventor： Vlad Fruchter ,  Nishant Sitapara ,  Javid Jaffari ,  Shrirang Madhav Yardi ,  Bardia Zandian

IPC: G06F1/28 ,  G02B27/01 ,  G05F1/66

CPC classification number: G06F1/28 ,  G02B27/017 ,  G05F1/66

Abstract: Systems and methods for peak power control include control circuitry which identifies a condition for a device. The control circuitry can apply the condition for the device to one or more models maintained for a plurality of device processing units of the device to determine one or more performance characteristics for the plurality of processing units. The control circuitry can distribute power credits to the plurality of device processing units of the device according to the determined performance characteristics for the plurality of device processing units, to manage a respective peak power for each respective device processing unit according to a number of the power credits distributed to the respective device processing unit.

公开(公告)号：US20230044573A1

公开(公告)日：2023-02-09

申请号：US17937742

申请日：2022-10-03

Applicant: Meta Platforms Technologies, LLC

Inventor： Vlad Fruchter ,  Richard Lawrence Greene ,  Hideo Tamama

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16 ,  G06F9/50 ,  G06F12/0802 ,  G06F12/14

Abstract: In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.

公开(公告)号：US20250044850A1

公开(公告)日：2025-02-06

申请号：US18886572

申请日：2024-09-16

Applicant: Meta Platforms Technologies, LLC

Inventor： Vlad Fruchter ,  Nishant Sitapara ,  Javid Jaffari ,  Shrirang Madhav Yardi ,  Bardia Zandian

IPC: G06F1/28 ,  G02B27/01 ,  G05F1/66

Abstract: Systems and methods for peak power control include control circuitry which identifies a condition for a device. The control circuitry can apply the condition for the device to one or more models maintained for a plurality of device processing units of the device to determine one or more performance characteristics for the plurality of processing units. The control circuitry can distribute power credits to the plurality of device processing units of the device according to the determined performance characteristics for the plurality of device processing units, to manage a respective peak power for each respective device processing unit according to a number of the power credits distributed to the respective device processing unit.

公开(公告)号：US12165334B2

公开(公告)日：2024-12-10

申请号：US17393636

申请日：2021-08-04

Applicant: Meta Platforms Technologies, LLC

Inventor： Ohad Meitav ,  Vlad Fruchter ,  Jeremy Snodgrass

IPC: G06T7/215 ,  G02B27/00 ,  G02B27/01 ,  G06T7/11 ,  G06T7/194 ,  G06V10/25

Abstract: A method for obtaining multiple frames of image data includes obtaining a first frame of image data of an entirety of a field of view by a camera sensor. The method also includes defining one or more regions of the field of view using the first frame of image data. The method includes determining at least one of a frame rate and an image capture resolution for each of the one or more regions. The method includes operating the camera sensor to obtain partial frames of image data by obtaining image data of the one or more regions of the field of view according to at least one of the frame rate and the image capture resolution, and re-constructing one or more full frames from partial frames of image data.

公开(公告)号：US20240220779A1

公开(公告)日：2024-07-04

申请号：US18527063

申请日：2023-12-01

Applicant: Meta Platforms Technologies, LLC

Inventor： Vignesh Vivekraja ,  Tomonari Tohara ,  Reza Tusi ,  Abuduwaili Tuoheti ,  Javid Jaffari ,  Vlad Fruchter ,  David Vakrat ,  Ohad Meitav

IPC: G06N3/0464 ,  G06F7/544 ,  G06F17/15 ,  H03H17/02

CPC classification number: G06N3/0464 ,  G06F7/5443 ,  G06F17/153 ,  H03H17/02

Abstract: In one embodiment, a system comprising a processor and a non-transitory memory coupled to the processor comprising instructions executable by the processor. The processor, comprising an internal memory; a Multiply-Accumulate (MAC) array; a first vector register array; a second vector register array; and a third vector register array, is operable when executing instructions to transfer weights for M filters and an input activation tensor from an external memory to the internal memory, insert paddings to the input activation tensor in the internal memory based on first configuration parameters, configure the MAC array to a required shape based on second configuration parameters for convolution operations between the input activation tensor and the M filters, and calculate a row of the output activation tensor by performing the convolution operations on corresponding R rows of the input activation tensor with the M filters, wherein R is a filter height.