公开(公告)号：US20240385674A1

公开(公告)日：2024-11-21

申请号：US18547130

申请日：2023-02-10

Applicant: MediaTek Inc.

Inventor： Chien-Nan Lin ,  You-Ming Tsao ,  Yung-Hsin Chu ,  An-Li Wang ,  Yu-Ting Kuo

IPC: G06F1/324 ,  A63F13/77

Abstract: A computing system performs balanced power management based on requirements of graphics scenes in a video game. Based on the requirements of the graphics scenes, the system selects one or more performance metrics to reduce in real-time, where the performance metrics are indicators of video game quality. The system compares estimated power consumption with a power budget after reducing the one or more performance metrics. Based on the requirements of the graphics scenes, the system further selects one or more quality enhancers to activate in real-time while keeping the estimated power consumption within the power budget. Each quality enhancer enhances the video game with respect to a performance metric. The system then displays the video game enhanced by the one or more quality enhancers.

公开(公告)号：US11436483B2

公开(公告)日：2022-09-06

申请号：US16246884

申请日：2019-01-14

Applicant: MediaTek Inc.

Inventor： Yu-Ting Kuo ,  Chien-Hung Lin ,  Shao-Yu Wang ,  ShengJe Hung ,  Meng-Hsuan Cheng ,  Chi-Ta Wu ,  Henrry Andrian ,  Yi-Siou Chen ,  Tai-Lung Chen

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06F12/084 ,  G06F17/15

Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.

公开(公告)号：US09613392B2

公开(公告)日：2017-04-04

申请号：US14475593

申请日：2014-09-03

Applicant: MEDIATEK INC.

Inventor： Yu-Ting Kuo

IPC: G06T1/00 ,  G06T1/20 ,  G06T11/40 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005

Abstract: A method for performing graphics processing of a graphics system in an electronic device and an associated apparatus are provided, where the method includes the steps of: configuring a configurable hardware of the graphics system to be a vertex processing (VP) path in a specific processing phase; utilizing the VP path to perform VP-related tile-based rendering (TBR) operations; configuring the configurable hardware of the graphics system to be a pixel processing (PP) path in another processing phase; and utilizing the PP path to perform PP-related TBR operations. For example, after performing VP-related TBR operations of a specific frame of a plurality of frames is completed, PP-related TBR operations of the specific frame are performed, where after performing the PP-related TBR operations of the specific frame is completed, VP-related TBR operations of another frame of the plurality of frames are performed.

公开(公告)号：US20190220742A1

公开(公告)日：2019-07-18

申请号：US16246884

申请日：2019-01-14

Applicant: MediaTek Inc.

Inventor： Yu-Ting Kuo ,  Chien-Hung Lin ,  Shao-Yu Wang ,  ShengJe Hung ,  Meng-Hsuan Cheng ,  Chi-Ta Wu ,  Henrry Andrian ,  Yi-Siou Chen ,  Tai-Lung Chen

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.

公开(公告)号：US20160063663A1

公开(公告)日：2016-03-03

申请号：US14475593

申请日：2014-09-03

Applicant: MEDIATEK INC.

Inventor： Yu-Ting Kuo

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005

Abstract: A method for performing graphics processing of a graphics system in an electronic device and an associated apparatus are provided, where the method includes the steps of: configuring a configurable hardware of the graphics system to be a vertex processing (VP) path in a specific processing phase; utilizing the VP path to perform VP-related tile-based rendering (TBR) operations; configuring the configurable hardware of the graphics system to be a pixel processing (PP) path in another processing phase; and utilizing the PP path to perform PP-related TBR operations. For example, after performing VP-related TBR operations of a specific frame of a plurality of frames is completed, PP-related TBR operations of the specific frame are performed, where after performing the PP-related TBR operations of the specific frame is completed, VP-related TBR operations of another frame of the plurality of frames are performed.

Abstract translation: 提供了一种用于在电子设备和相关联的设备中执行图形系统的图形处理的方法，其中该方法包括以下步骤：将图形系统的可配置硬件配置为特定处理中的顶点处理（VP）路径 相; 利用VP路径执行VP相关的基于瓦片的渲染（TBR）操作; 在另一个处理阶段将图形系统的可配置硬件配置为像素处理（PP）路径; 并利用PP路径执行PP相关的TBR操作。 例如，在完成了多个帧的特定帧的VP相关TBR操作之后，执行特定帧的PP相关TBR操作，其中在执行特定帧的PP相关TBR操作完成之后， 执行多个帧的另一帧的与VP相关的TBR操作。