公开(公告)号：US11436483B2

公开(公告)日：2022-09-06

申请号：US16246884

申请日：2019-01-14

Applicant: MediaTek Inc.

Inventor： Yu-Ting Kuo ,  Chien-Hung Lin ,  Shao-Yu Wang ,  ShengJe Hung ,  Meng-Hsuan Cheng ,  Chi-Ta Wu ,  Henrry Andrian ,  Yi-Siou Chen ,  Tai-Lung Chen

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06F12/084 ,  G06F17/15

Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.

公开(公告)号：US20250045095A1

公开(公告)日：2025-02-06

申请号：US18364742

申请日：2023-08-03

Applicant: MediaTek Inc.

Inventor： Shi-Yi Ou ,  Tun Yi Chang ,  Henrry Andrian ,  Jeng-Yun Hsu

IPC: G06F9/48 ,  G06N3/063

Abstract: Deep learning accelerator (DLA) hardware performs task preemption. The DLA hardware executes a first task by using a neural network of multiple layers on a given input. In response to a stop command from a DLA driver to stop execution of the first task, the DLA hardware completes a current operation of the neural network and sending an interrupt request (IRQ) to the DLA driver. The DLA hardware then receives a second task from the DLA driver. The DLA hardware executes the second task to completion before resuming the execution of the first task.

公开(公告)号：US20190220742A1

公开(公告)日：2019-07-18

申请号：US16246884

申请日：2019-01-14

Applicant: MediaTek Inc.

Inventor： Yu-Ting Kuo ,  Chien-Hung Lin ,  Shao-Yu Wang ,  ShengJe Hung ,  Meng-Hsuan Cheng ,  Chi-Ta Wu ,  Henrry Andrian ,  Yi-Siou Chen ,  Tai-Lung Chen

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.