Voltage generating circuit and ESD protecting method

    公开(公告)号:US10305480B2

    公开(公告)日:2019-05-28

    申请号:US15275482

    申请日:2016-09-26

    Applicant: MEDIATEK INC.

    Inventor: Wen-Yi Lin

    Abstract: A voltage generating circuit comprising: a first switch circuit, operating in a first power domain; a second switch circuit, operating in a second power domain; a first transistor of first type, comprising a control terminal coupled to the first switch circuit and the second first switch circuit, wherein the control terminal of the first transistor of first type is coupled to a predetermined voltage source via the first switch circuit if the first switch circuit is active, wherein the control terminal of the first transistor of first type is coupled to the predetermined voltage source via the second switch circuit if the second switch circuit is active; and an output circuit, coupled to the first transistor of first type and operating in the second power domain.

    VOLTAGE GENERATING CIRCUIT AND ESD PROTECTING METHOD

    公开(公告)号:US20170170830A1

    公开(公告)日:2017-06-15

    申请号:US15275482

    申请日:2016-09-26

    Applicant: MEDIATEK INC.

    Inventor: Wen-Yi Lin

    CPC classification number: H03K19/00361 H01L27/0266 H03K19/018521

    Abstract: A voltage generating circuit comprising: a first switch circuit, operating in a first power domain; a second switch circuit, operating in a second power domain; a first transistor of first type, comprising a control terminal coupled to the first switch circuit and the second first switch circuit, wherein the control terminal of the first transistor of first type is coupled to a predetermined voltage source via the first switch circuit if the first switch circuit is active, wherein the control terminal of the first transistor of first type is coupled to the predetermined voltage source via the second switch circuit if the second switch circuit is active; and an output circuit, coupled to the first transistor of first type and operating in the second power domain.

    Flip-flop circuit and scan chain using the same

    公开(公告)号:US10126363B2

    公开(公告)日:2018-11-13

    申请号:US15647485

    申请日:2017-07-12

    Applicant: MEDIATEK INC.

    Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.

    STANDARD CELL CIRCUITRIES
    5.
    发明申请
    STANDARD CELL CIRCUITRIES 审中-公开
    标准电路电路

    公开(公告)号:US20170018572A1

    公开(公告)日:2017-01-19

    申请号:US15168507

    申请日:2016-05-31

    Applicant: MediaTek Inc.

    CPC classification number: H01L27/0629 H03K19/00361 H03K19/00369

    Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

    Abstract translation: 标准单元电路包括标准单元单元和第一电阻设备。 标准单元单元耦合到至少一个电阻器。 第一电阻器件耦合到标准单元单元并且提供用于第一电流流过的第一电流路径。

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