公开(公告)号：US10126363B2

公开(公告)日：2018-11-13

申请号：US15647485

申请日：2017-07-12

Applicant: MEDIATEK INC.

Inventor： Wen-Yi Lin ,  Girishankar Gurumurthy

IPC: G01R31/3185 ,  H03K3/027 ,  H03K19/20 ,  G01R31/3177 ,  G01R31/317

Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.