-
公开(公告)号：US20190173441A1
公开(公告)日：2019-06-06
申请号：US16268002
申请日：2019-02-05
申请人： Maxlinear, Inc.
发明人： Abhishek Jajoo , Vamsi Paidi
摘要： Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.
-
公开(公告)号：US09923547B2
公开(公告)日：2018-03-20
申请号：US15236372
申请日：2016-08-12
申请人： Maxlinear, Inc.
CPC分类号： H03H11/30 , H03B1/00 , H03B5/00 , H03B5/1237 , H03B25/00 , H03B27/00 , H03B2200/0072
摘要： Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable. The impedance matching elements may include a resistor coupled to a bias voltage VDD and to a common node with a capacitor that is coupled to ground, where the common node is coupled to one of the inductors. The output device may include a prescaler that is an integer or fractional frequency-N divider, or a buffer. The respective drivers coupled to each of the plurality of VCOs may be configured to provide a constant output power no matter which of said plurality of VCOs is enabled.
-
公开(公告)号：US09762181B2
公开(公告)日：2017-09-12
申请号：US15224530
申请日：2016-07-30
申请人： Maxlinear, Inc.
发明人： Abhishek Jajoo , Pawan Tiwari , Vamsi Paidi
CPC分类号： H03B5/20 , H03B27/00 , H03B2200/009 , H03L7/23
摘要： Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.
-
4.发明申请公开(公告)号：US20170047932A1
公开(公告)日：2017-02-16
申请号：US15236369
申请日：2016-08-12
申请人： Maxlinear, Inc.
发明人： Sangeetha Gopalakrishnan , Sheng Ye , Vamsi Paidi
CPC分类号： H03L7/085 , H03L7/093 , H03L7/099 , H03L7/1974 , H03L7/1976
摘要： Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.
摘要翻译： 锁相环（PLL）中采样环路滤波器的方法和系统可以包括锁相环（PLL），其包括相位频率检测器，包括多个电容器和至少一个开关的采样环路滤波器，多个电压 耦合到所述采样环路滤波器的受控振荡器（VCO）和分频器。 当提供给采样环路滤波器中的多个电容器中的第一电容器的电荷的平均值为零时，PLL产生至少一个时钟信号，并且采样的环路滤波器对来自相位频率检测器的输出信号进行采样。 分频器可以是分数N分频器。 所述采样环路滤波器中的第二开关可以具有与至少一个开关的开关时间不重叠的开关时间。 电容器可以从第二开关的每个端子耦合到地。
-
5.发明授权公开(公告)号：US09419569B2
公开(公告)日：2016-08-16
申请号：US14260214
申请日：2014-04-23
申请人： Maxlinear, Inc.
发明人： Abhishek Jajoo , Vamsi Paidi
CPC分类号： H03F3/45179 , H03F1/523 , H03F3/195 , H03F3/45188 , H03F2200/171 , H03F2200/222 , H03F2200/294 , H03F2200/336 , H03F2200/451 , H03F2203/45166 , H03F2203/45386 , H03F2203/45464
摘要： Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.
摘要翻译： 用于Ku波段的伪差分低噪声放大器的方法和系统可以包括集成在半导体管芯上的低噪声放大器（LNA），其中LNA包括集成在半导体管芯上的嵌入式电感尾部的差分对晶体管。 嵌入式电感器尾部可以包括：第一电感器，其具有电容耦合到差分对晶体管的第一晶体管的栅极端子的第一端子和耦合到第二，第三和第四电感器的第一电感器的第二端子。 第二电感器可以耦合到差分对晶体管的第一晶体管的源极端子，第四电感器可以耦合到差分对晶体管的第二晶体管的源极端子，并且第三电感器可以电容耦合到 差分对晶体管的第二晶体管的栅极端子以及接地。 第二电感器可以嵌入在第一电感器内。
-
6.发明申请METHOD AND SYSTEM FOR A PSEUDO-DIFFERENTIAL LOW-NOISE AMPLIFIER AT KU-BAND 有权在KU带上的PSEUDO-DIFFERENTIAL低噪声放大器的方法和系统公开(公告)号：US20140320206A1
公开(公告)日：2014-10-30
申请号：US14260214
申请日：2014-04-23
申请人： Maxlinear, Inc.
发明人： Abhishek Jajoo , Vamsi Paidi
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F1/523 , H03F3/195 , H03F3/45188 , H03F2200/171 , H03F2200/222 , H03F2200/294 , H03F2200/336 , H03F2200/451 , H03F2203/45166 , H03F2203/45386 , H03F2203/45464
摘要： Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.
摘要翻译： 用于Ku波段的伪差分低噪声放大器的方法和系统可以包括集成在半导体管芯上的低噪声放大器（LNA），其中LNA包括集成在半导体管芯上的嵌入式电感尾部的差分对晶体管。 嵌入式电感器尾部可以包括：第一电感器，其具有电容耦合到差分对晶体管的第一晶体管的栅极端子的第一端子和耦合到第二，第三和第四电感器的第一电感器的第二端子。 第二电感器可以耦合到差分对晶体管的第一晶体管的源极端子，第四电感器可以耦合到差分对晶体管的第二晶体管的源极端子，并且第三电感器可以电容耦合到 差分对晶体管的第二晶体管的栅极端子以及接地。 第二电感器可以嵌入在第一电感器内。
-
公开(公告)号：US10651806B2
公开(公告)日：2020-05-12
申请号：US16268002
申请日：2019-02-05
申请人： Maxlinear, Inc.
发明人： Abhishek Jajoo , Vamsi Paidi
摘要： Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.
-
公开(公告)号：US10404260B2
公开(公告)日：2019-09-03
申请号：US15906578
申请日：2018-02-27
申请人： Maxlinear, Inc.
摘要： Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.
-
9.发明授权公开(公告)号：US10148300B2
公开(公告)日：2018-12-04
申请号：US15887605
申请日：2018-02-02
申请人： Maxlinear, Inc.
发明人： Raja Pullela , Wenjian Chen , Vamsi Paidi
摘要： Methods and systems for a configurable low-noise amplifier with programmable band-selection filters may comprise a receiver with a low-noise amplifier (LNA) with first and second input terminals and differential output terminals; a low pass filter operably coupled to the LNA; a high pass filter operably coupled to the second input terminal of the LNA; and a signal source input coupled to the low pass filter and the high pass filter. The LNA may be operable to receive signals in a pass band of the high pass filter and a pass band of the low pass filter. The receiver may be operable to amplify input signals in the pass band of a first filter but not signals in the pass band of the second filter by operably coupling the second to ground.
-
10.发明申请公开(公告)号：US20180159572A1
公开(公告)日：2018-06-07
申请号：US15887605
申请日：2018-02-02
申请人： Maxlinear, Inc.
发明人： Raja Pullela , Wenjian Chen , Vamsi Paidi
CPC分类号： H04B1/16 , H03F1/565 , H03F3/195 , H03F2200/06 , H03F2200/165 , H03F2200/171 , H03F2200/294 , H03F2200/429 , H03F2200/451 , H03F2203/7209 , H03G5/28 , H03H7/0115 , H04B1/005
摘要： Methods and systems for a configurable low-noise amplifier with programmable band-selection filters may comprise a receiver with a low-noise amplifier (LNA) with first and second input terminals and differential output terminals; a low pass filter operably coupled to the LNA; a high pass filter operably coupled to the second input terminal of the LNA; and a signal source input coupled to the low pass filter and the high pass filter. The LNA may be operable to receive signals in a pass band of the high pass filter and a pass band of the low pass filter. The receiver may be operable to amplify input signals in the pass band of a first filter but not signals in the pass band of the second filter by operably coupling the second to ground.
-
-
-
-
-
-
-
-
-
搜索结果
44 条记录 (耗时 0.02 秒)
