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    Semiconductor memory, memory device, and memory card
    1.
    发明授权
    Semiconductor memory, memory device, and memory card 失效
    半导体存储器，存储器件和存储卡

    公开(公告)号：US06477671B2

    公开(公告)日：2002-11-05

    申请号：US09845350

    申请日：2001-05-01

    申请人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    发明人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    IPC分类号： G11C2900

    CPC分类号： G11C29/70 ,  G11C29/88

    摘要： A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

    摘要翻译： 一种半导体存储器（1），包括设置有大量存储单元的多个存储块（2和3），数据输入/输出缓冲器（7）和用于控制数据的重写和读取的第一控制装置（11） 为存储单元设置有用于指定部分缺陷存储块的第一存储装置（30）和用于根据地址信号检测由第一存储装置指定的缺陷存储块的存取的检测装置（32）。 在这种情况下，当检测装置检测到对缺陷存储器的访问时，第一控制装置禁止用于数据重写操作的指令的数据重写操作，并且禁止数据输入/输出缓冲器的数据输出操作用于指令 数据读取操作。 禁止功能使得可以仅通过组合具有不可弥补缺陷的半导体存储器来提供具有与无缺陷半导体存储器的兼容性的存储器件，而不固定特定地址输入端子的电平，以便保持有缺陷的存储块非选择性。

    Semiconductor memory, memory device, and memory card
    2.
    发明授权
    Semiconductor memory, memory device, and memory card 有权
    半导体存储器，存储器件和存储卡

    公开(公告)号：US06266792B1

    公开(公告)日：2001-07-24

    申请号：US09427068

    申请日：1999-10-26

    申请人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    发明人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    IPC分类号： G11C2900

    CPC分类号： G11C29/70 ,  G11C29/88

    摘要： A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data-input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

    摘要翻译： 一种半导体存储器（1），包括设置有大量存储单元的多个存储块（2和3），数据输入/输出缓冲器（7）和用于控制重写和读取的第一控制装置 存储单元的数据设置有用于指定部分缺陷存储块的第一存储装置（30）和用于根据地址信号检测由第一存储装置指定的缺陷存储块的访问的检测装置（32）。 在这种情况下，当检测装置检测到对缺陷存储器的访问时，第一控制装置禁止用于数据重写操作的指令的数据重写操作，并且禁止数据输入/输出缓冲器的数据输出操作用于指令 数据读取操作。 禁止功能使得可以仅通过组合具有不可弥补缺陷的半导体存储器来提供具有与无缺陷半导体存储器的兼容性的存储器件，而不固定特定地址输入端子的电平，以便保持有缺陷的存储块非选择性。

    Semiconductor memory, memory device, and memory card
    3.
    发明授权
    Semiconductor memory, memory device, and memory card 有权
    半导体存储器，存储器件和存储卡

    公开(公告)号：US06757853B2

    公开(公告)日：2004-06-29

    申请号：US10244539

    申请日：2002-09-17

    申请人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    发明人： Masashi Wada ,  Takao Okubo ,  Takeshi Furuno

    IPC分类号： G11C2900

    CPC分类号： G11C29/70 ,  G11C29/88

    摘要： A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.

    摘要翻译： 提供封装在一个封装中的存储器件，其包括集成在一个半导体衬底中的第一数据端子，第一地址端子，状态端子和存储器芯片，存储器芯片之一是非易失性存储器。 每个存储芯片包括数据终端和地址终端。 每个存储器芯片的数据端子连接到第一数据端子，并且每个存储器芯片的地址端子连接到第一地址端子。 状态终端被配置为输出指示何时非易失性存储器处于就绪状态或处于忙状态的状态信号。

    Model-based job supporting system and method thereof
    6.
    发明授权
    Model-based job supporting system and method thereof 失效
    基于模型的工作支持系统及其方法

    公开(公告)号：US6141665A

    公开(公告)日：2000-10-31

    申请号：US800380

    申请日：1997-02-14

    申请人： Hirotaka Hara ,  Sanya Uehara ,  Takao Okubo ,  Nobuyuki Kanaya ,  Yuuji Hotta

    发明人： Hirotaka Hara ,  Sanya Uehara ,  Takao Okubo ,  Nobuyuki Kanaya ,  Yuuji Hotta

    IPC分类号： G06Q10/10 ,  G06F15/00 ,  G06F17/60

    CPC分类号： G06Q10/10

    摘要： A job model with which an organization model representing an organization structure, a document model representing a document structure, and a work model representing a work procedure are correlated, is stored independent from a service model defining each service. When a service is performed, with reference to the job model corresponding to the service model, a service executing module causes a tool control module to control a tool. Thus, the required service is accomplished.

    摘要翻译： 与代表每个服务的服务模型独立地存储表示组织结构的组织模型，表示文档结构的文档模型和表示工作过程的工作模型相关联的作业模型。 当执行服务时，参考与服务模型对应的作业模型，服务执行模块使得工具控制模块控制工具。 因此，完成所需的服务。