公开(公告)号：US20090129147A1

公开(公告)日：2009-05-21

申请号：US12126686

申请日：2008-05-23

申请人： Masaru YANO ,  Akira OGAWA

发明人： Masaru YANO ,  Akira OGAWA

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/28

摘要： Structures, methods, and systems for multiple programming of spare memory region for nonvolatile memory are disclosed. In one embodiment, a nonvolatile memory system comprises a main memory cell array, a spare memory cell array, and a memory controller that divides the spare memory cell array into at least a first region and a second region. The system further comprises a selection module for selecting the main memory cell array and the first region to write data and the first reference cell to write first reference data associated with the data during an initial data writing operation and for selecting the second region to write additional data and the second reference cell to write second reference data associated with the additional data during an additional data writing operation.

摘要翻译： 公开了用于非易失性存储器的备用存储器区域的多次编程的结构，方法和系统。 在一个实施例中，非易失性存储器系统包括主存储单元阵列，备用存储单元阵列和将备用存储单元阵列划分成至少第一区域和第二区域的存储器控​​制器。 该系统还包括选择模块，用于选择主存储单元阵列和第一区域以写入数据，第一参考单元在初始数据写入操作期间写入与数据相关联的第一参考数据，并且用于选择第二区域以写入额外的数据 数据和第二参考单元以在附加数据写入操作期间写入与附加数据相关联的第二参考数据。

公开(公告)号：US20130064016A1

公开(公告)日：2013-03-14

申请号：US13413527

申请日：2012-03-06

申请人： Akira OGAWA ,  Masaru YANO

发明人： Akira OGAWA ,  Masaru YANO

IPC分类号： G11C16/28

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

公开(公告)号：US20130155774A1

公开(公告)日：2013-06-20

申请号：US13610368

申请日：2012-09-11

申请人： Akira OGAWA ,  Masaru YANO

发明人： Akira OGAWA ,  Masaru YANO

IPC分类号： G11C16/28

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

摘要翻译： 本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列中的核心单元的第一电流 - 电压转换电路，连接到参考单元的第二电流 - 电压转换电路 参考单元数据线，感测来自第一电流 - 电压转换电路的输出和来自第二电流 - 电压转换电路的输出的读出放大器，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路 以及如果在对所述参考单元数据线预充电期间所述参考单元数据线处的电压电平低于所述预定电压电平，则对所述参考单元数据线充电的充电电路。 根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

公开(公告)号：US20120069676A1

公开(公告)日：2012-03-22

申请号：US13253634

申请日：2011-10-05

申请人： Akira OGAWA ,  Masaru YANO

发明人： Akira OGAWA ,  Masaru YANO

IPC分类号： G11C16/26

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

摘要翻译： 本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列中的核心单元的第一电流 - 电压转换电路，连接到参考单元的第二电流 - 电压转换电路 参考单元数据线，感测来自第一电流 - 电压转换电路的输出和来自第二电流 - 电压转换电路的输出的读出放大器，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路 以及如果在对所述参考单元数据线预充电期间所述参考单元数据线处的电压电平低于所述预定电压电平，则对所述参考单元数据线充电的充电电路。 根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

公开(公告)号：US20110182116A1

公开(公告)日：2011-07-28

申请号：US12901990

申请日：2010-10-11

申请人： Akira OGAWA ,  Masaru YANO

发明人： Akira OGAWA ,  Masaru YANO

IPC分类号： G11C16/28 ,  H01L21/02

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

公开(公告)号：US20120121366A1

公开(公告)日：2012-05-17

申请号：US13283986

申请日：2011-10-28

申请人： Akira OGAWA

发明人： Akira OGAWA

IPC分类号： B62D43/04 ,  B66D1/00

CPC分类号： B62D43/04

摘要： A spare wheel holding apparatus includes a device for winding up a spare wheel with a suspending member. The device includes a rotation restricting plate and a rotation restricting pin having a projecting pin portion. When a winding-off force is applied to the suspending member, the rotation restricting plate abuts on the projecting pin portion, thereby stopping winding-off of the suspending member. A suspending member breakage preventing mechanism also uses the rotation restricting pin as a safety pin. If the winding-off force is larger than that in normal, the projecting pin portion is broken at a root portion, the suspending member is wound off, thereby preventing breakage. The root portion has a smaller thickness than a tip end portion of the projecting pin portion.

摘要翻译： 备用轮保持装置包括用于将备用轮与悬挂构件卷起的装置。 该装置包括旋转限制板和具有突出销部分的旋转限制销。 当向悬挂构件施加释放力时，旋转限制板抵接在突出销部上，从而阻止悬挂构件的卷绕。 悬挂构件防破坏机构也使用旋转限制销作为安全销。 如果释放力大于正常情况，则突出销部分在根部处断裂，悬挂构件被卷绕，从而防止断裂。 根部具有比突出销部分的顶端部分更小的厚度。

公开(公告)号：US20130279253A1

公开(公告)日：2013-10-24

申请号：US13619273

申请日：2012-09-14

申请人： Akira OGAWA ,  Yoshichika NAKAYA

发明人： Akira OGAWA ,  Yoshichika NAKAYA

IPC分类号： G11C16/08

CPC分类号： G11C8/12 ,  G11C7/16 ,  G11C7/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor chip D1 of a flash memory which is stacked together with other semiconductor chips D2˜DN to form a multi-chip package (MCP), including a memory cell array 20 of the flash memory for storing an ID code and an upper address, wherein the ID code is written into the a fuse data region 20F of the memory cell array 20 before the assembly process. According to the invention, ID codes and upper addresses can be assigned and written to each of the semiconductor chips of a multi-chip package easily without increasing the size of the semiconductor chips in comparison with the prior art.

摘要翻译： 闪存的半导体芯片D1与其他半导体芯片D2〜DN堆叠以形成多芯片封装（MCP），包括用于存储ID代码和高地址的闪速存储器的存储单元阵列20， 其中在组装过程之前将ID代码写入存储单元阵列20的熔丝数据区域20F。 根据本发明，与现有技术相比，可以容易地将ID码和上位地址分配并写入多芯片封装的每个半导体芯片，而不增加半导体芯片的尺寸。

公开(公告)号：US20120197172A1

公开(公告)日：2012-08-02

申请号：US13361178

申请日：2012-01-30

申请人： Akira OGAWA

发明人： Akira OGAWA

IPC分类号： A61F5/00

CPC分类号： A61F5/11 ,  A61K31/00

摘要： A device includes: a cylindrical body formed of an elastic material; and a slit formed along a longitudinal direction of the cylindrical body from one end to an opposite end of the cylindrical body, a distal end of a nail being inserted to be held in the slit. The cylindrical body includes: plural pairs of holding teeth plurally divided in the longitudinal direction of the cylindrical body by dividing grooves formed from the slit along a circumferential direction of the cylindrical body such that the holding teeth of each pair are opposed to each other across the slit to hold the distal end of the nail; and coupling pieces configured to couple adjacent ones of the holding teeth on an opposite side of the slit.

摘要翻译： 一种装置包括：由弹性材料形成的圆筒体; 以及沿筒体的长度方向从圆柱体的一端到另一端形成的狭缝，将钉子的前端插入以保持在狭缝中。 圆柱体包括：多个保持齿沿着圆柱体的圆周方向沿圆周方向分隔成多个沿圆柱体的纵向方向分割的多个保持齿，使得每对的保持齿彼此相对 狭缝夹住指甲的远端; 以及联接件，其构造成在狭缝的相对侧上将相邻的保持齿联接。

公开(公告)号：US20130249595A1

公开(公告)日：2013-09-26

申请号：US13549204

申请日：2012-07-13

申请人： Akira OGAWA

发明人： Akira OGAWA

IPC分类号： H03K19/094 ,  H03K19/02

CPC分类号： G11C16/06 ,  G11C7/1084 ,  G11C7/1087 ,  G11C16/30

摘要： A level shift circuit, for outputting a data output signal with a second level via an output inverter after a data input signal with a first level is stored in a latch, includes a level set circuit, when the output data signal outputs with a low level, setting the output data signal to a low level in response to a change of the input data signal. The level set circuit is connected to an output terminal of the output inverter, and has an NMOS transistor having a drain electrode and a source electrode coupled to a ground, wherein the NMOS transistor turns on in response to the input data signal with a high level.

摘要翻译： 一种电平移位电路，用于在具有第一电平的数据输入信号被存储在锁存器中之后经由输出反相器输出具有第二电平的数据输出信号，包括电平设置电路，当输出数据信号以低电平输出时 ，响应于输入数据信号的改变将输出数据信号设置为低电平。 电平设定电路连接到输出反相器的输出端子，并且具有NMOS晶体管，其具有耦合到地的漏电极和源电极，其中NMOS晶体管响应于具有高电平的输入数据信号而导通 。

公开(公告)号：US20110302058A1

公开(公告)日：2011-12-08

申请号：US13153501

申请日：2011-06-06

申请人： Masaki HASHIURA ,  Gen AOYAMA ,  Yoshinari SAWATA ,  Akira OGAWA

发明人： Masaki HASHIURA ,  Gen AOYAMA ,  Yoshinari SAWATA ,  Akira OGAWA

IPC分类号： G06Q30/00

CPC分类号： G06Q30/00 ,  G06Q30/0641

摘要： Provided is a content playback apparatus capable of presenting, while playback a digital content, selling price information for the digital content being reproduced. The content playback apparatus is provided with a content playback portion which reproduces a digital content, a selling price information obtaining portion which obtains selling price information concerning the digital content, and a selling price information presentation portion which presents the obtained selling price information. The selling price information presentation portion presents, during playback of a digital content, the selling price information concerning the digital content.

摘要翻译： 提供一种能够在播放数字内容时呈现正在再现的数字内容的销售价格信息的内容再现装置。 内容再现装置设置有再现数字内容的内容再现部分，获取关于数字内容的销售价格信息的销售价格信息获取部分和呈现所获得的销售价格信息的销售价格信息呈现部分。 销售价格信息呈现部分在数字内容的回放期间呈现关于数字内容的销售价格信息。