公开(公告)号：US11967587B2

公开(公告)日：2024-04-23

申请号：US18108520

申请日：2023-02-10

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Dan Azeroual ,  Liav Ben Artsi

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L24/72 ,  H01L24/90 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/107 ,  H01L2225/1094

Abstract: A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.

公开(公告)号：US11581292B2

公开(公告)日：2023-02-14

申请号：US16898261

申请日：2020-06-10

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Dan Azeroual ,  Liav Ben Artsi

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

公开(公告)号：US09921596B2

公开(公告)日：2018-03-20

申请号：US14575334

申请日：2014-12-18

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Liav Ben Artsi

IPC: H02H9/00 ,  G05F1/613 ,  G11C5/14 ,  G11C7/02

CPC classification number: G05F1/613 ,  G11C5/14 ,  G11C7/02

Abstract: A power supply noise reduction circuit and a power supply noise reduction method are provided. An integrated circuit includes an input node configured to receive a signal via a transmission line. The integrated circuit also includes termination circuitry configured to electrically couple the input node to a power rail of the integrated circuit. The integrated circuit further includes a circuit component coupled to the power rail. The circuit component is configured to bleed off a portion of current on the power rail based on a determination that a voltage on the power rail meets or exceeds a high voltage threshold. The circuit component is also configured to bleed off a smaller portion of the current on the power rail based on a determination that the voltage on the power rail is less than the high voltage threshold.

公开(公告)号：US20150177773A1

公开(公告)日：2015-06-25

申请号：US14575334

申请日：2014-12-18

Applicant: Marvell Israel (M.I.S.L) LTD.

Inventor： Liav Ben Artsi

IPC: G05F5/00

CPC classification number: G05F1/613 ,  G11C5/14 ,  G11C7/02

Abstract: A power supply noise reduction circuit and a power supply noise reduction method are provided. An integrated circuit includes an input node configured to receive a signal via a transmission line. The integrated circuit also includes termination circuitry configured to electrically couple the input node to a power rail of the integrated circuit. The integrated circuit further includes a circuit component coupled to the power rail. The circuit component is configured to bleed off a portion of current on the power rail based on a determination that a voltage on the power rail meets or exceeds a high voltage threshold. The circuit component is also configured to bleed off a smaller portion of the current on the power rail based on a determination that the voltage on the power rail is less than the high voltage threshold.

Abstract translation: 提供电源降噪电路和电源降噪方法。 集成电路包括被配置为经由传输线接收信号的输入节点。 集成电路还包括被配置为将输入节点电耦合到集成电路的电源轨的终端电路。 集成电路还包括耦合到电力轨的电​​路部件。 电路部件被配置为基于电力轨上的电压达到或超过高电压阈值的判断来泄漏电力轨上的一部分电流。 电路部件还被配置为基于电力轨上的电压小于高电压阈值的判断来泄漏电力轨上电流的较小部分。

公开(公告)号：US11789067B1

公开(公告)日：2023-10-17

申请号：US17170622

申请日：2021-02-08

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Liav Ben Artsi

IPC: H01L21/67 ,  G01R31/28

CPC classification number: G01R31/2896 ,  H01L21/67288

Abstract: An integrated circuit (IC) is manufactured and is mounted in an IC package. A processor of a measurement system determines a reference value of a physical layer (PHY) parameter at a second test point on a test fixture based on one or more model values, specified by an Ethernet communication standard, corresponding to a first test point on the test fixture corresponding to a contact on the IC package and one or more measured test fixture parameters characterizing a channel connecting the first test point to the second test point on the test fixture. The processor then determines whether the PHY parameter at the first test point on the IC package complies with the Ethernet communication standard based on i) the reference value of the PHY parameter and ii) a measured value of the PHY parameter obtained from a measurement of the PHY parameter at the second test point.

公开(公告)号：US09143368B1

公开(公告)日：2015-09-22

申请号：US14558140

申请日：2014-12-02

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Liav Ben Artsi ,  Miki Moyal

IPC: H04L27/01 ,  H04L25/03

CPC classification number: H04L25/03146

Abstract: Systems and methods are provided for an equalizer. An equalizer includes a first voltage correcting circuit configured to correct a communication signal by applying a first variable corrective voltage to the communication signal, the first corrective voltage having a voltage level selected according to a first adjustable granularity. A second voltage correcting circuit is configured to further correct the communication signal by applying a second variable corrective voltage to the communication signal, the second corrective voltage having a voltage level selected according to a second adjustable granularity that is different from the first adjustable granularity.

Abstract translation: 为均衡器提供了系统和方法。 均衡器包括：第一电压校正电路，被配置为通过对通信信号施加第一可变校正电压来校正通信信号，第一校正电压具有根据第一可调颗粒度选择的电压电平。 第二电压校正电路被配置为通过对通信信号施加第二可变校正电压来进一步校正通信信号，第二校正电压具有根据与第一可调粒度不同的第二可调粒度选择的电压电平。

公开(公告)号：US11917749B1

公开(公告)日：2024-02-27

申请号：US17655912

申请日：2022-03-22

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Dan Azeroual ,  Liav Ben Artsi

IPC: H05K1/02 ,  H01L23/66 ,  H05K3/40 ,  H01L23/50

CPC classification number: H05K1/0222 ,  H01L23/50 ,  H01L23/66 ,  H05K1/0228 ,  H05K3/40 ,  H01L2223/6638

Abstract: An integrated circuit package, including a circuit board, signal pins extending orthogonally to the circuit board surface, and grouped into a plurality of differential signal pin pairs, each signal pin pair positioned at a vertex of an array of orthogonal rows and columns, wherein each signal pin pair includes a positive and a negative signal pin. The plurality of signal pin pairs includes a first subset of signal pin pairs wherein the positive and the negative signal pins are arranged in an orientation along a line parallel to rows of the array and a second subset of signal pin pairs in which the positive and the negative signal pins are arranged in an orientation along a line parallel to columns of the array. For each signal pin pair in one of the first and second subsets, each nearest signal pin pairs belong to another of the first and second subsets.

公开(公告)号：US20240008180A1

公开(公告)日：2024-01-04

申请号：US18344511

申请日：2023-06-29

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Liav Ben Artsi ,  Noam Kutscher

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/0233 ,  H05K3/429 ,  H05K2201/096

Abstract: A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.

公开(公告)号：US08502342B1

公开(公告)日：2013-08-06

申请号：US13684331

申请日：2012-11-23

Applicant: Marvell Israel (M.I.S.L.) Ltd.

Inventor： Liav Ben Artsi

IPC: H01L29/00

CPC classification number: H01L29/00 ,  H01L23/5222 ,  H01L23/5223 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Circuits, architectures, a system and methods for reducing the effect(s) of cross talk in neighboring I/O signal paths. The circuitry includes input/output (I/O) pads having I/O signal lines coupled thereto, and a capacitor having terminals coupled to the I/O pads and/or signal lines. The method includes transmitting or receiving a signal along a first I/O signal line in an integrated circuit, the first I/O signal line communicating with a first I/O pad on the integrated circuit, and the integrated circuit having a second I/O signal line communicating with a second I/O pad; and capacitively coupling the first signal to the second I/O pad and/or the second I/O signal line, to reduce the effect(s) of cross talk in the second I/O signal line. The present invention can significantly reduce the effects of cross talk in neighboring I/O signal paths, for both input and output signals.

Abstract translation: 电路，架构，减少相邻I / O信号路径中串扰影响的系统和方法。 电路包括具有与其耦合的I / O信号线的输入/输出（I / O）焊盘，以及具有耦合到I / O焊盘和/或信号线的端子的电容器。 该方法包括沿着集成电路中的第一I / O信号线发送或接收信号，第一I / O信号线与集成电路上的第一I / O焊盘通信，并且集成电路具有第二I / O信号线与第二I / O接口通信; 并且将第一信号电容耦合到第二I / O焊盘和/或第二I / O信号线，以减少第二I / O信号线中串扰的影响。 本发明可以显着地减少输入和输出信号在相邻I / O信号路径中串扰的影响。