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1.发明授权Data transmission apparatus having frequency synthesizer with integer division factor, corresponding method, and data transmission system 有权具有整数分频因子的频率合成器，相应的方法和数据传输系统的数据传输装置公开(公告)号：US09042505B2
公开(公告)日：2015-05-26
申请号：US14065436
申请日：2013-10-29
Applicant: MEDIATEK INC.
Inventor： Chi-Feng Lin , Kung-Yen Hsu , Yu-Bang Nian
Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.
Abstract translation: 提供了设置在以不同数据速率操作的两个网络层内的数据传输设备。 数据传输装置耦合到时钟发生器，该时钟发生器为下层网络层提供参考时钟，并且以一个整数分频因子耦合到一个频率合成器，该系数根据参考时钟和整数产生上层网络层的分时钟 分裂因子 数据传输装置包括第一处理电路和第二处理电路。 对应于上层网络层的第一处理电路通过使用分频时钟作为其操作频率来接收和发送数据。 对应于较低网络层的第二处理电路通过使用参考时钟作为编码数据的操作频率从第一处理电路接收和发送数据。 分频时钟由具有整数除法因子的频率合成器产生。
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2.发明申请NETWORK DEVICE AND METHOD FOR OUTPUTTING DATA TO BUS WITH DATA BUS WIDTH AT EACH CYCLE BY GENERATING END OF PACKET AND START OF PACKET AT DIFFERENT CYCLES 有权网络设备和方法，用于通过生成分组结束并在不同周期开始分组，将数据输出到总线，数据总线宽度公开(公告)号：US20150016466A1
公开(公告)日：2015-01-15
申请号：US14258021
申请日：2014-04-22
Applicant: Mediatek Inc.
Inventor： Chi-Feng Lin , Wei-Jen Chen
IPC: H04L12/701
CPC classification number: H04L69/324 , H04L12/40 , H04L47/38 , H04L47/6245
Abstract: A method used in a network device for outputting data to a bus with a data bus width at each cycle includes: using a packet generator for generating idle data after an end of packet for a packet at a cycle and generating a start of packet for a next packet at a different cycle; and using an inter-packet gap (IPG) generator for receiving data transmitted from the packet generator, dynamically writing the received data into the buffer, and inserting a gap of idle data between the end of packet and the start of packet according to the end of packet and the idle data generated by the packet generator.
Abstract translation: 一种网络设备中用于向每个周期的数据总线宽度总线输出数据的网络设备的方法包括：使用分组生成器，用于在一个周期的分组的分组结束之后生成空闲数据，并产生一个分组的开始 下一个包在不同的周期; 并且使用分组间间隔（IPG）发生器来接收从分组生成器发送的数据，将接收到的数据动态地写入缓冲器，并根据结束在分组结束和分组开始之间插入空闲数据的间隙 的分组和由分组生成器生成的空闲数据。
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Patent Agency Ranking
公开(公告)号：US20170180519A1
公开(公告)日：2017-06-22
申请号：US15450006
申请日：2017-03-05
Applicant: MEDIATEK INC.
Inventor： Chi-Feng Lin , Wei-Jen Chen
IPC: H04L29/08 , H04L12/40 , H04L12/863 , H04L12/811
CPC classification number: H04L69/324 , H04L12/40 , H04L47/38 , H04L47/6245
Abstract: A method used in a network device for outputting data to a bus with a data bus width at each cycle includes: using a packet generating circuit for generating idle data after an end of packet for a packet at a cycle and generating a start of packet for a next packet at a different cycle; and using an inter-packet gap (IPG) generating circuit for receiving data transmitted from the packet generating circuit, dynamically writing the received data into the buffer, and inserting a gap of idle data between the end of packet and the start of packet according to the end of packet and the idle data generated by the packet generating circuit.
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公开(公告)号：US09628396B2
公开(公告)日：2017-04-18
申请号：US14258021
申请日：2014-04-22
Applicant: MEDIATEK INC.
Inventor： Chi-Feng Lin , Wei-Jen Chen
IPC: H04L12/701 , H04L12/811
CPC classification number: H04L69/324 , H04L12/40 , H04L47/38 , H04L47/6245
Abstract: A method used in a network device for outputting data to a bus with a data bus width at each cycle includes: using a packet generator for generating idle data after an end of packet for a packet at a cycle and generating a start of packet for a next packet at a different cycle; and using an inter-packet gap (IPG) generator for receiving data transmitted from the packet generator, dynamically writing the received data into the buffer, and inserting a gap of idle data between the end of packet and the start of packet according to the end of packet and the idle data generated by the packet generator.
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5.发明申请DATA TRANSMISSION APPARATUS HAVING FREQUENCY SYNTHESIZER WITH INTEGER DIVISION FACTOR, CORRESPONDING METHOD, AND DATA TRANSMISSION SYSTEM 有权具有整数分解因子的频率合成器的数据传输装置，相应的方法和数据传输系统公开(公告)号：US20150121120A1
公开(公告)日：2015-04-30
申请号：US14065436
申请日：2013-10-29
Applicant: MEDIATEK INC.
Inventor： Chi-Feng Lin , Kung-Yen Hsu , Yu-Bang Nian
IPC: G06F1/08
Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.
Abstract translation: 提供了设置在以不同数据速率操作的两个网络层内的数据传输设备。 数据传输装置耦合到时钟发生器，该时钟发生器为下层网络层提供参考时钟，并且以一个整数分频因子耦合到一个频率合成器，该系数根据参考时钟和整数产生上层网络层的分时钟 分裂因子 数据传输装置包括第一处理电路和第二处理电路。 对应于上层网络层的第一处理电路通过使用分频时钟作为其操作频率来接收和发送数据。 对应于较低网络层的第二处理电路通过使用参考时钟作为编码数据的操作频率从第一处理电路接收和发送数据。 分频时钟由具有整数除法因子的频率合成器产生。
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公开(公告)号：US09998575B2
公开(公告)日：2018-06-12
申请号：US15450006
申请日：2017-03-05
Applicant: MEDIATEK INC.
Inventor： Chi-Feng Lin , Wei-Jen Chen
IPC: H04L29/08 , H04L12/40 , H04L12/863 , H04L12/811
CPC classification number: H04L69/324 , H04L12/40 , H04L47/38 , H04L47/6245
Abstract: A method used in a network device for outputting data to a bus with a data bus width at each cycle includes: using a packet generating circuit for generating idle data after an end of packet for a packet at a cycle and generating a start of packet for a next packet at a different cycle; and using an inter-packet gap (IPG) generating circuit for receiving data transmitted from the packet generating circuit, dynamically writing the received data into the buffer, and inserting a gap of idle data between the end of packet and the start of packet according to the end of packet and the idle data generated by the packet generating circuit.
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公开(公告)号：US09787434B2
公开(公告)日：2017-10-10
申请号：US14567172
申请日：2014-12-11
Applicant: MediaTek Inc.
Inventor： Chi-Feng Lin , Yu-Bang Nian
CPC classification number: H04L1/0061 , H03M13/091 , H04L1/0045
Abstract: A communication device and associated method is provided. The communication device includes: a controller; a packet buffer, configured to store a current packet segment and a previous packet segment of an incoming packet; and a plurality of cyclic redundancy check (CRC) circuits, wherein each CRC circuit is individually fed with a portion of the current packet segment and/or a portion of the previous packet segment in a respective cycle of the incoming packet, and an initial value, wherein the plurality of CRC circuits are arranged in parallel.
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