公开(公告)号：US20030201521A1

公开(公告)日：2003-10-30

申请号：US10131485

申请日：2002-04-25

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC: H01L023/02

CPC classification number: H01L23/5389 ,  H01L23/49816 ,  H01L24/19 ,  H01L25/0652 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.

Abstract translation: 半导体封装装置包括至少具有空腔或槽的载体。 至少芯片具有背面和具有多个第一接合焊盘的活性表面。 芯片固定在腔体上以露出活性表面。 第一绝缘层位于有源表面和载体上，载体包括连接到第一焊盘并经由第一绝缘层的第一通孔导体。 第一绝缘层上的多层结构包括多个导电布线，其中第二通孔导体和第二绝缘层，暴露的球垫和倒装芯片。 第一通孔导体与导电布线，第二通孔导体，暴露的滚珠焊盘和倒装芯片焊盘电连接。 第一焊球固定到球垫上，并且至少第二芯片通过多个第二焊球固定到倒装芯片焊盘。

公开(公告)号：US20040021230A1

公开(公告)日：2004-02-05

申请号：US10211278

申请日：2002-08-05

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC: H01L023/48

CPC classification number: H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacking multi-chip device comprises a substrate having a recess, stud bumpers or conductive stud strips thereon. A low die has a back surface affixed in the recess or the substrate, and has a first active surface comprising a plurality of bonding pads. The bonding pads of the low die have a set of elongate conductors connected to the substrate. An upper die has a back surface and a second active surface comprising a plurality of bonding pads. The bonding pads of the upper die have a plurality of stud bumpers connected to the stud bumpers, conductive stud strips, or the substrate by the method of reflow or anti-tropic conductive film. The second active surface is faced towards said first active surface and is offset stacked atop the low die to expose all bonding pads.

Abstract translation: 堆叠式多芯片装置包括具有凹部的基板，其上的螺柱缓冲器或导电柱条。 低模具具有固定在凹部或基板中的背面，并具有包括多个键合垫的第一活性表面。 低压模的接合焊盘具有连接到基板的一组细长导体。 上模具有后表面和包括多个接合焊盘的第二有源表面。 上模的接合焊盘具有通过回流或反向导电膜的方法连接到螺柱缓冲器，导电螺柱条或基板的多个螺柱缓冲器。 第二有源表面面向所述第一有源表面，并且被偏置堆叠在低压模上方以暴露所有接合焊盘。

公开(公告)号：US20020158316A1

公开(公告)日：2002-10-31

申请号：US09842133

申请日：2001-04-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jui-Chung Lee ,  Chen-Jung Tsai ,  Chih-Wen Lin

IPC: H01L023/495 ,  H01L023/02

CPC classification number: H01L23/49575 ,  H01L23/49513 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a structure of a stacked-type multi-chip stack package of the leadframe. The shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).

Abstract translation: 本发明提供了引线框的堆叠型多芯片堆叠封装的结构。 可以调节阶梯状内部引线的形状，以便堆叠芯片的高度和数量，并且可以匹配不同的焊接技术。 用于形成本结构的方法可以通过可见的设备和材料容易地进行，并且本结构可以提高接合过程的可靠性。 本发明可以堆叠多芯片（多于两个）。

公开(公告)号：US20030183917A1

公开(公告)日：2003-10-02

申请号：US10105155

申请日：2002-03-26

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC: H01L023/02

CPC classification number: H01L23/3128 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.

Abstract translation: 层叠的半导体封装装置至少由包括衬底的堆叠式多芯片器件构成。 第一芯片具有面向衬底的后表面，并且活性表面包括多个接合焊盘，其具有连接到衬底的第一组细长导体。 第二芯片具有另一个背面，另一个活性表面包括多个键合焊盘，其具有连接到衬底的第二组细长导体。 第二芯片的有源表面面向所述第一芯片的有源表面，并且堆叠在第一芯片的顶部，以暴露所有焊盘。 第一芯片和第二芯片的面对面布置可以降低整个包装高度。

公开(公告)号：US20030151143A1

公开(公告)日：2003-08-14

申请号：US10074052

申请日：2002-02-14

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC: H01L023/48

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure is on the first insulating layer, which comprises conductive layout lines, second plating through holes therein, and a second insulating layer and exposed ball pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, and the exposed ball pads. A plurality of solder balls are affixed to the ball pads. Such architecture integrates the redistribution and fan-out process, which simplifies the conventional process for flip-chip ball grid array.

Abstract translation: 半导体封装装置包括至少具有空腔或槽的载体。 至少芯片具有背面和具有多个第一接合焊盘的活性表面。 芯片固定在腔体上以露出活性表面。 第一绝缘层位于有源表面和载体上，其包括通过连接到第一焊盘并经由第一绝缘层的第一电镀通孔。 多层结构在第一绝缘层上，其包括导电布线，其中通孔中的第二电镀，以及第二绝缘层和暴露的球垫。 第一电镀通孔与导电布线，第二电镀通孔和暴露的球垫电连接。 多个焊球固定在球垫上。 这种架构集成了再分配和扇出过程，这简化了倒装芯片球栅阵列的常规工艺。

公开(公告)号：US20020180021A1

公开(公告)日：2002-12-05

申请号：US10132157

申请日：2002-04-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wen Lin ,  Chen-Jung Tsai ,  Jui-Chung Lee

IPC: H01L021/50

CPC classification number: H01L24/85 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49113 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85191 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2224/45099

Abstract: The present invention provides a structure and a method for multi-chip stack package. The present invention uses the liquid insulating epoxy to adhere and stack chips. The liquid insulating epoxy is filled the space between chips and metal wires bonded thereon and the liquid insulating epoxy is higher than the high of the arc of those metal wires, so it can increase the reliability of stacking and bonding process. The present invention can stack multi-chip (more than two) bycontrolling the arc height of the wire and the thickness of the chip. The present can easily perform by visible equipment and materials.

Abstract translation: 本发明提供了一种用于多芯片堆叠封装的结构和方法。 本发明使用液体绝缘环氧树脂粘合和堆叠芯片。 液体绝缘环氧树脂填充在其上的芯片和金属线之间的空间，并且液体绝缘环氧树脂高于那些金属线的电弧的高度，因此可以提高堆叠和接合过程的可靠性。 本发明可以通过控制电线的电弧高度和芯片的厚度来堆叠多芯片（多于两个）。 现在可以通过可见的设备和材料轻松执行。