公开(公告)号：US20040253784A1

公开(公告)日：2004-12-16

申请号：US10893659

申请日：2004-07-16

Applicant: LSI Logic Corporation

Inventor： Hong-Qiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay

IPC: H01L021/8238

CPC classification number: H01L21/76829 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76832

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

公开(公告)号：US20030084587A1

公开(公告)日：2003-05-08

申请号：US10322974

申请日：2002-12-18

Applicant: LSI Logic Corporation

Inventor： Kiran Kumar ,  Zhihai Wang ,  Rudy Rios ,  Wilbur G. Catabay ,  Richard D. Schinella

IPC: F26B019/00 ,  F26B025/06 ,  C23F001/00 ,  H01L021/306 ,  F26B003/00 ,  F26B009/00 ,  F26B013/00 ,  F26B013/06

CPC classification number: H01L21/67167 ,  C23C14/566 ,  C23C16/4401 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/76802 ,  H01L21/76843

Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber. The substrate transfer chamber maintains a third environment of high cleanliness around the substrate, and transfers the substrate into more than one substrate processing chambers, where the substrate is selectively transferred into and out of the more than one substrate processing chambers without leaving the high cleanliness of the third environment. The substrate transfer chamber also selectively passes the substrate to the substrate pass through chamber when the substrate pass through chamber has formed the high cleanliness of the second environment. The substrate pass through chamber also receives the substrate from the substrate transfer chamber, and selectively passes the substrate to the substrate load chamber when the substrate load chamber has formed the intermediate cleanliness of the first environment. The substrate load chamber receives the substrate from the substrate pass through chamber, and selectively passes the substrate out of the substrate load chamber and into the ambient contaminant laden environment when the substrate load chamber is not open to the substrate pass through chamber.

公开(公告)号：US20040238960A1

公开(公告)日：2004-12-02

申请号：US10802522

申请日：2004-03-17

Applicant: LSI Logic Corporation

Inventor： Valeriy Sukharev ,  Wilbur G. Catabay ,  Hongqiang Lu

IPC: H01L021/44

CPC classification number: H01L21/76849 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract translation: 一种在集成电路中形成金属互连的方法。 在集成电路上的电介质结构上形成铜层，其中电介质结构具有较高的电平。 铜层被平坦化为不高于电介质结构的上层，而不降低电介质结构的上层。 在所有铜层上形成导电覆盖层，而不在任何电介质结构上形成覆盖层。

公开(公告)号：US20040157425A1

公开(公告)日：2004-08-12

申请号：US10772133

申请日：2004-02-03

Applicant: LSI Logic Corporation

Inventor： Wilbur G. Catabay ,  Zhihai Wang ,  Ping Li

IPC: H01L021/44

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization. Other embodiments include providing a substrate in a processing chamber and forming a copper seed layer on the substrate. The seed layer is implanted with barrier materials to form an implanted seed layer followed by bulk copper-containing layer formation. The substrate is annealed to form a final barrier layer. In a related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a copper seed layer on the first barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer. In yet another related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a second barrier layer on the first layer. A copper seed layer is formed on the second barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer.

Abstract translation: 本发明的实施例包括一种形成具有双层铜阻挡层的铜互连的方法。 该方法包括以下步骤：在处理室中提供衬底，所述衬底具有低K电介质绝缘层和绝缘层中的开口。 在绝缘层和开口中形成钽/氮化钽的第一阻挡层。 在第一阻挡层上形成第二阻挡层。 第二阻挡层由选自钯，铬，钽，镁和钼的材料组成。 在第二阻挡层上形成铜籽晶层，在籽晶层上形成体铜层。 将衬底退火并进行可包括平坦化的进一步加工。 其他实施例包括在处理室中提供衬底并在衬底上形成铜籽晶层。 种子层被植入阻挡材料以形成植入的种子层，然后形成大块含铜层。 将衬底退火以形成最终的阻挡层。 在相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一阻挡层上形成铜籽晶层的步骤。 在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。 在另一相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一层上形成第二阻挡层的步骤。 在第二阻挡层上形成铜籽晶层。 在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。

公开(公告)号：US20030064593A1

公开(公告)日：2003-04-03

申请号：US10268735

申请日：2002-10-10

Applicant: LSI Logic Corporation

Inventor： Kiran Kumar ,  Zhihai Wang ,  Wilbur G. Catabay

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L21/28247 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/3211 ,  Y10S438/914 ,  Y10S438/957

Abstract: A method for creating a highly reflective surface on an electroplated conduction layer. A barrier layer is deposited on a substrate using a self ionized plasma deposition process. The barrier layer has a thickness of no more than about one hundred angstroms. An adhesion layer is deposited on the barrier layer, using a self ionized plasma deposition process. A seed layer is deposited on the adhesion layer, also using a self ionized plasma deposition process, at a bias of no les than about one hundred and fifty watts. The combination of the barrier layer, adhesion layer, and seed layer is at times referred to herein as the barrier seed layer. The conduction layer is electroplated on the seed layer, thereby forming the highly reflective surface on the conduction layer, where the highly reflective surface has a reflectance of greater than about seventy percent.

Abstract translation: 一种在电镀导电层上形成高反射面的方法。 使用自电离等离子体沉积工艺将阻挡层沉积在衬底上。 阻挡层的厚度不大于约一百埃。 使用自电离等离子体沉积工艺在阻挡层上沉积粘附层。 种子层沉积在粘附层上，也使用自电离等离子体沉积工艺，偏压不大于约一百五十瓦。 阻挡层，粘合层和种子层的组合在本文中有时被称为阻挡种子层。 将导电层电镀在种子层上，由此在导电层上形成高反射表面，其中高反射表面的反射率大于约百分之七十。

公开(公告)号：US20030064588A1

公开(公告)日：2003-04-03

申请号：US10238073

申请日：2002-09-09

Applicant: LSI Logic Corporation

Inventor： Wilbur G. Catabay ,  Zhihai Wang

IPC: H01L021/44

CPC classification number: H01L21/76846

Abstract: A method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.