公开(公告)号：US08274269B2

公开(公告)日：2012-09-25

申请号：US12487596

申请日：2009-06-18

申请人： Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Yong Seo Koo

发明人： Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Yong Seo Koo

IPC分类号： G05F1/00

CPC分类号： H02M1/08 ,  H02M2001/0032 ,  Y02B70/16

摘要： Provided are a switching circuit and a small-size high-efficiency direct current-to-direct current (DC-DC) converter for portable devices including the same. Using dynamic threshold-complementary metal oxide semiconductor (DT-CMOS) transistors having dynamic threshold voltages as a switching device, the switching circuit maintains a low threshold voltage in a normal mode to improve current drivability while reducing conduction loss, and maintains a high threshold voltage in a standby mode to minimize power consumption. When the switching circuit is employed in a DC-DC converter, power conversion efficiency can be improved by reducing conduction loss in the normal mode, and power consumption can be minimized in the standby mode. Consequently, the DC-DC converter can maximize a use time of a battery of a portable device and can be useful in power supplies of portable devices that are gradually being miniaturized.

摘要翻译： 提供了一种用于包括其的便携式设备的开关电路和小尺寸高效率直流 - 直流（DC-DC）转换器。 使用具有动态阈值电压的动态阈值互补金属氧化物半导体（DT-CMOS）晶体管作为开关器件，开关电路在正常模式下维持低阈值电压，从而改善电流驱动能力，同时降低导通损耗，并保持高阈值电压 处于待机模式以最小化功耗。 当在DC-DC转换器中采用开关电路时，可以通过降低正常模式下的导通损耗来提高功率转换效率，并且在待机模式下功耗可以最小化。 因此，DC-DC转换器可以使便携式设备的电池的使用时间最大化，并且可以用于逐渐小型化的便携式设备的电源。

公开(公告)号：US20110148534A1

公开(公告)日：2011-06-23

申请号：US12878697

申请日：2010-09-09

申请人： Hui Dong LEE ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Hui Dong LEE ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1293

摘要： An LC voltage-controlled oscillator (VCO) is provided. The LC VCO includes an LC resonant circuit including at least one inductor whose both terminals are connected to output nodes and at least one capacitor connected in parallel with the inductor, and an amplifier circuit including at least one pair of switching transistors. Here, drains of the pair of switching transistors are connected to the output nodes respectively, and gates of the switching transistors are connected with the drains through a variable capacitance block exhibiting different characteristics according to an input signal.

摘要翻译： 提供了一个LC压控振荡器（VCO）。 LC VCO包括LC谐振电路，其包括至少一个电感器，其两个端子连接到输出节点和与电感器并联连接的至少一个电容器，以及包括至少一对开关晶体管的放大器电路。 这里，一对开关晶体管的漏极分别连接到输出节点，并且开关晶体管的栅极通过根据输入信号呈现不同特性的可变电容块与漏极连接。

公开(公告)号：US07683706B2

公开(公告)日：2010-03-23

申请号：US12195202

申请日：2008-08-20

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/02

CPC分类号： H03F3/005

摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

摘要翻译： 提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到 输入电容器的估计输出电压值而不是0。 因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

公开(公告)号：US20080068237A1

公开(公告)日：2008-03-20

申请号：US11695143

申请日：2007-04-02

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/168

摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure. The multi-bit pipeline ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected with an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein N is an integer greater than or equal to 1 and K is an integer greater than or equal to 2.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.

摘要翻译： 提供了具有共享放大器结构的多位流水线模数转换器（ADC）。 多位流水线ADC包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压并消除输入电压的采样误差; 第一至第K级的N位闪存ADC接收模拟信号，将其转换为数字信号并输出​​数字信号; 第一到第K级的N位乘法数模转换器（MDAC）将从N位闪存ADC输出的数字信号与前级的输出信号之间的差值转换成模拟信号并输出​​模拟信号; 以及在第一时钟与第一级的N位MDAC的输出和第二时钟的SHA的输出连接的三级放大器，其中N是大于或等于1的整数，并且K是 整数大于或等于2.在多位流水线ADC中，可以在消耗大量功率的SHA和第一级的MDAC之间共享放大器，从而可以降低功耗和芯片尺寸。

公开(公告)号：US07583219B2

公开(公告)日：2009-09-01

申请号：US12027495

申请日：2008-02-07

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim ,  Seung Chul Lee

IPC分类号： H03M1/38

CPC分类号： H03M1/1245 ,  H03M1/002 ,  H03M1/44

摘要： Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

摘要翻译： 提供了没有前端采样保持放大器（SHA）的管线模数转换器（ADC）及其控制方法。 该方法包括以下步骤：在ADC和包括在第一级中的残余信号发生器同时对模拟输入信号进行采样，并分别产生第一采样值和第二采样值; 在剩余信号发生器处保持​​第二采样值，并且同时在ADC处放大并转换第一采样值为相应的数字代码; 以及在剩余信号发生器处产生使用数字码的残留信号。 流水线ADC和控制相同的方法最小化了通过去除前端SHA引起的采样失配，从而确保了没有前端SHA的稳定性能。 由于不使用前端SHA，因此可以减少芯片尺寸和功耗，并提高ADC的性能。

公开(公告)号：US20090091383A1

公开(公告)日：2009-04-09

申请号：US12195202

申请日：2008-08-20

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03F1/00

CPC分类号： H03F3/005

摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

摘要翻译： 提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到 输入电容器的估计输出电压值而不是0。 因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

公开(公告)号：US07397409B2

公开(公告)日：2008-07-08

申请号：US11695143

申请日：2007-04-02

申请人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Young Deuk Jeon ,  Seung Chul Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/168

摘要： A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.

摘要翻译： 具有共享放大器结构的多位流水线模数转换器（ADC）包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压并去除输入电压的采样误差; 第一至第K级的N位闪存ADC接收模拟信号，将其转换为数字信号并输出​​数字信号; 第一到第K级的N位乘法数模转换器（MDAC）将从N位闪存ADC输出的数字信号与前级的输出信号之间的差值转换成模拟信号并输出​​模拟信号; 以及三级放大器，在第一时钟连接到第一级的N位MDAC的输出，在第二时钟连接到SHA的输出，其中，间隔N> =且K> = 2。 放大器可以在第一级的SHA和MDAC之间共享，从而降低功耗和芯片尺寸。 在多位流水线ADC中，放大器可以在消耗大量功率的SHA和第一级的MDAC之间共享，从而可以降低功耗和芯片尺寸。

公开(公告)号：US08217728B2

公开(公告)日：2012-07-10

申请号：US12878697

申请日：2010-09-09

申请人： Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： H03B5/12 ,  H03C3/22

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1293

摘要： An LC voltage-controlled oscillator (VCO) is provided. The LC VCO includes an LC resonant circuit including at least one inductor whose both terminals are connected to output nodes and at least one capacitor connected in parallel with the inductor, and an amplifier circuit including at least one pair of switching transistors. Here, drains of the pair of switching transistors are connected to the output nodes respectively, and gates of the switching transistors are connected with the drains through a variable capacitance block exhibiting different characteristics according to an input signal.

摘要翻译： 提供了一个LC压控振荡器（VCO）。 LC VCO包括LC谐振电路，其包括至少一个电感器，其两个端子连接到输出节点和与电感器并联连接的至少一个电容器，以及包括至少一对开关晶体管的放大器电路。 这里，一对开关晶体管的漏极分别连接到输出节点，并且开关晶体管的栅极通过根据输入信号呈现不同特性的可变电容块与漏极连接。

公开(公告)号：US08446194B2

公开(公告)日：2013-05-21

申请号：US13275753

申请日：2011-10-18

申请人： Seok Ju Yun ,  Hui Dong Lee ,  Kwi Dong Kim ,  Jong-Kee Kwon

发明人： Seok Ju Yun ,  Hui Dong Lee ,  Kwi Dong Kim ,  Jong-Kee Kwon

IPC分类号： H03L7/06

CPC分类号： H03L7/1976 ,  H03L7/0891

摘要： Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio.

摘要翻译： 提供了一种扩频时钟发生电路。 扩频时钟发生电路包括：相位检测器，从外部接收参考频率信号，并检测参考频率信号与分频信号之间的相位差; 输出与所述相位检测器的检测结果对应的振荡信号的压控振荡器; 主分压器，通过将振荡信号的频率除以主分频比来产生分频信号; 以及产生可变计数值的分频比控制器，通过根据计数值进行Δ-Σ调制而产生分分割比，并根据分分割比调节主分频比。

公开(公告)号：US20120105114A1

公开(公告)日：2012-05-03

申请号：US13275753

申请日：2011-10-18

申请人： Seok Ju YUN ,  Hui Dong Lee ,  Kwi Dong Kim ,  Jong-Kee Kwon

发明人： Seok Ju YUN ,  Hui Dong Lee ,  Kwi Dong Kim ,  Jong-Kee Kwon

IPC分类号： H03L7/06

CPC分类号： H03L7/1976 ,  H03L7/0891

摘要： Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio.

摘要翻译： 提供了一种扩频时钟发生电路。 扩频时钟发生电路包括：相位检测器，从外部接收参考频率信号，并检测参考频率信号与分频信号之间的相位差; 输出与所述相位检测器的检测结果对应的振荡信号的压控振荡器; 主分压器，通过将振荡信号的频率除以主分频比来产生分频信号; 以及产生可变计数值的分频比控制器，通过根据计数值进行Δ-Σ调制而产生分分割比，并根据分分割比调节主分频比。