公开(公告)号：US06333262B1

公开(公告)日：2001-12-25

申请号：US09636558

申请日：2000-08-11

申请人： Kuen-Syh Tseng ,  Ruoh-Haw Chang ,  Shu-Jen Chen

发明人： Kuen-Syh Tseng ,  Ruoh-Haw Chang ,  Shu-Jen Chen

IPC分类号： H01L2044

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming silicide on a semiconductor wafer. The semiconductor wafer includes a doped silicon layer on a predetermined area of the semiconductor wafer, a metal layer positioned on the doped silicon layer, and a barrier layer covering the metal layer. A first rapid thermal processing (RTP) step is performed to make portions of the metal layer react with silicon inside the doped silicon layer so as to form a transitional silicide. The barrier layer and the portions of the metal layer that have not reacted with silicon are then removed. A dielectric layer is formed on the transitional silicide. Finally, a second rapid thermal processing (RTP) step is performed to make the transitional silicide react with portions of the doped silicon layer so as to form the silicide.

摘要翻译： 一种在半导体晶片上形成硅化物的方法。 半导体晶片包括在半导体晶片的预定区域上的掺杂硅层，位于掺杂硅层上的金属层和覆盖金属层的阻挡层。 执行第一快速热处理（RTP）步骤以使金属层的部分与掺杂硅层内的硅反应，以形成过渡硅化物。 然后除去未与硅反应的阻挡层和金属层的部分。 在过渡硅化物上形成介电层。 最后，进行第二快速热处理（RTP）步骤以使过渡硅化物与掺杂硅层的部分反应以形成硅化物。

公开(公告)号：US06303043B1

公开(公告)日：2001-10-16

申请号：US09348407

申请日：1999-07-07

申请人： Wei-Shiau Chen ,  Ruoh-Haw Chang ,  Shu-Jen Chen

发明人： Wei-Shiau Chen ,  Ruoh-Haw Chang ,  Shu-Jen Chen

IPC分类号： H01L2100

CPC分类号： H01L21/76801 ,  G02F1/133553 ,  G02F1/136277 ,  H01L21/76832 ,  H01L21/76834 ,  Y10S438/954

摘要： A method of fabricating a preserve layer. A top metallic layer is formed over the substrate. Portions of the metallic layer and the substrate are removed to form a trench. A conformal pad oxide layer is formed over the substrate. A conformal first nitride layer is formed on the pad oxide layer. A spin-on glass layer is formed on the first nitride layer to fill the trench. An etching back step is performed to remove a portion of the spin-on glass layer. The remaining spin-on glass layer fills the trench to the surface of the first nitride layer above the top metallic layer. An oxide layer is formed over the substrate. A second nitride layer is formed on the oxide layer. A preserve layer comprising the pad oxide layer, the first nitride layer, the oxide layer, and the second nitride layer is formed.

摘要翻译： 一种保护层的制造方法。 顶层金属层形成在衬底上。 去除部分金属层和基底以形成沟槽。 在衬底上形成保形衬垫氧化物层。 在焊盘氧化物层上形成共形的第一氮化物层。 在第一氮化物层上形成旋涂玻璃层以填充沟槽。 执行蚀刻返回步骤以去除旋涂玻璃层的一部分。 剩余的旋涂玻璃层将沟槽填充到顶部金属层上方的第一氮化物层的表面。 在衬底上形成氧化物层。 在氧化物层上形成第二氮化物层。 形成包括衬垫氧化物层，第一氮化物层，氧化物层和第二氮化物层的保护层。

公开(公告)号：US6150264A

公开(公告)日：2000-11-21

申请号：US075420

申请日：1998-05-08

申请人： Shu-Jen Chen ,  Ruoh-Haw Chang ,  Chih-Ching Hsu

发明人： Shu-Jen Chen ,  Ruoh-Haw Chang ,  Chih-Ching Hsu

IPC分类号： H01L21/285 ,  H01L21/44

CPC分类号： H01L21/28518

摘要： The invention relates to a method for manufacturing of a titanium self-aligned silicide (Salicide). This process includes of forming a metal layer over the surfaces of the semiconductor substrate and the gate electrode. Then, a rapid thermal process is performed with three stages to form the salicide, for example, titanium silicide, at the interface between the titanium and silicon, namely on the surfaces of the gate electrode and source/drain region. The rapid thermal process with three stages includes using the first stage with the first temperature to form the early titanium silicide having the C49 phase. The temperature is raised to a second temperature and the RTA process is performed with nitrogen gases to transform the high resistance phase C49 of the titanium nitride into a low resistance phase C54 in the second stage. Then, the temperature is rapidly raised to a third temperature to transform the C49 phase into the C54 phase completely and to prevent the agglomeration phenomenon.

摘要翻译： 本发明涉及钛自对准硅化物（硅化物）的制造方法。 该方法包括在半导体衬底和栅电极的表面上形成金属层。 然后，以三个阶段进行快速热处理，以在钛和硅之间的界面，即在栅电极和源极/漏极区的表面上形成硅化物，例如硅化钛。 具有三个阶段的快速热处理包括使用具有第一温度的第一阶段形成具有C49相的早期硅化钛。 将温度升至第二温度，并用氮气进行RTA处理，以将氮化钛的高电阻相C49转化为第二阶段的低电阻相C54。 然后，将温度迅速升至第三温度，以使C49相完全转化为C54相，并防止凝聚现象。

公开(公告)号：US06390902B1

公开(公告)日：2002-05-21

申请号：US09875504

申请日：2001-06-06

申请人： Ruoh-Haw Chang ,  Hung-Yu Kuo ,  Yao-Hung Liu ,  De-Can Liao

发明人： Ruoh-Haw Chang ,  Hung-Yu Kuo ,  Yao-Hung Liu ,  De-Can Liao

IPC分类号： B24B500

CPC分类号： B24B53/017 ,  B24B53/003

摘要： The present invention provides a multi-conditioner arrangement of a CMP system. The CMP system according to the present invention comprises a polishing table, a polishing pad positioned on the polishing table, a plurality of carrier heads on the polishing pad functioning in holding semiconductor wafers, and a plurality of conditioners positioned between the two neighboring carrier heads on the polishing pad for recovering the surface texture of the polishing pad. Herein, a plurality of conditioners are in a one-to-one arrangement to a plurality of carrier heads, each conditioner producing a back and forth motion in a radiant direction. Therefore, the lifetime of the polishing pad is extended, the wafer-to-wafer difference is reduced, and spatial coverage is increased.

摘要翻译： 本发明提供一种CMP系统的多调节装置。 根据本发明的CMP系统包括抛光台，位于抛光台上的抛光垫，在保持半导体晶片的功能上的抛光垫上的多个载体头，以及位于两个相邻载体头之间的多个调节器 该抛光垫用于回收抛光垫的表面纹理。 这里，多个调节器与多个载体头一一对应地布置，每个调节器在辐射方向上产生前后运动。 因此，抛光垫的寿命延长，晶片与晶片的差异减小，空间覆盖率增加。