公开(公告)号：US20230169317A1

公开(公告)日：2023-06-01

申请号：US18059861

申请日：2022-11-29

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology (KAIST)

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: G06N3/063 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/6684 ,  H01L29/7839 ,  H01L29/7883 ,  H01L29/66825

Abstract: A neuromorphic devices may be formed having a three-dimensional stacked structure. The neuromorphic device may include a lower device formed on a substrate, an interlayer insulating layer formed on the substrate to cover the lower device, a synapse device having a Schottky barrier transistor structure formed on the interlayer insulating layer, and a vertical connection wiring formed in the interlayer insulating layer to electrically connect the lower device and the synapse device. The synapse device may include a channel, a source having a metal silicide forming a first Schottky junction with the channel, a drain having a metal silicide forming a second Schottky junction with the channel, a floating gate for a synaptic operation, and a control gate. The synapse device may be formed using only low-temperature processes performed at less than about 500° C.

公开(公告)号：US20220012576A1

公开(公告)日：2022-01-13

申请号：US17371364

申请日：2021-07-09

Applicant: Korea Advanced Institute Of Science And Technology

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN ,  Geon-Beom LEE ,  Jinki KIM

IPC: G06N3/063 ,  H01L29/872

Abstract: A neuromorphic synaptic device based on a charge trap and having linearity and symmetricity improved by using a schottky junction and a neuromorphic system using the same are provided. The neuromorphic synaptic device includes a body layer formed on a semiconductor substrate, a source and a drain formed at a left side and a right side, or an upper side and a lower side of the body layer, a contact metal to form a schottky junction by making contact with the source and the drain, a gate insulating layer formed on the body layer, and including an oxide layer and a charge storage layer, and a gate formed on the gate insulating layer.

公开(公告)号：US20240047600A1

公开(公告)日：2024-02-08

申请号：US17630463

申请日：2021-12-15

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN

IPC: H01L31/113 ,  G06N3/067

CPC classification number: H01L31/1136 ,  G06N3/067

Abstract: A transistor for implementing a photo-responsive neuronal device is disclosed. According to one example embodiment, the transistor includes a semiconductor substrate including a hole barrier region or an electron barrier region; a floating body extended in a horizontal direction on the hole barrier region or the electron barrier region; a source region and a drain region formed at both ends of the floating body; a gate insulating film formed on the floating body; and a gate region formed on the gate insulating film.

公开(公告)号：US20230153598A1

公开(公告)日：2023-05-18

申请号：US17976945

申请日：2022-10-31

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Inkyu PARK ,  Joon-Kyu HAN ,  Mingu KANG

IPC: G06N3/065 ,  A61B5/145

CPC classification number: G06N3/065 ,  A61B5/145

Abstract: The present disclosure relates to a gas-responsive neuron module including a resistive gas sensor for sensing gaseous molecules and converting the sensed gaseous molecules into an electrical signal, and a single transistor neuron composed of a source, a drain, and a gate, and a gas sensing system for sensing gas including the same, for implementing a high-integration and low-power neuromorphic electronic nose.

公开(公告)号：US20210097380A1

公开(公告)日：2021-04-01

申请号：US17037444

申请日：2020-09-29

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN ,  Gyeong Jun YUN

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/792 ,  H01L27/1157

Abstract: The present invention relates to a single transistor implementing a neuromorphic system capable of performing neuron and synaptic operations through the single transistor including a floating body layer and a charge storage layer and being implemented by a neuron device and a synaptic device which are co-integrated on the same plane, and the neuromorphic system using the same, and forms the single transistor including a hole barrier material layer formed on a substrate and including a hole barrier material or an electron barrier material, the floating body layer formed on the hole barrier material layer, a source and a drain formed on opposite sides of the floating body layer, a gate insulating layer formed on the floating body layer and including an oxide layer and the charge storage layer, and a gate formed on the gate insulating layer.