公开(公告)号：US06627506B2

公开(公告)日：2003-09-30

申请号：US09908277

申请日：2001-07-18

申请人： Kelin J. Kuhn ,  Ian R. Post

发明人： Kelin J. Kuhn ,  Ian R. Post

IPC分类号： H01L21331

CPC分类号： H01L21/3144 ,  H01L21/76232

摘要： The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.

公开(公告)号：US06368931B1

公开(公告)日：2002-04-09

申请号：US09536860

申请日：2000-03-27

申请人： Kelin J. Kuhn ,  Ian R. Post

发明人： Kelin J. Kuhn ,  Ian R. Post

IPC分类号： H01L21331

CPC分类号： H01L21/3144 ,  H01L21/76232

摘要： The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.

公开(公告)号：US06803285B2

公开(公告)日：2004-10-12

申请号：US10310281

申请日：2002-12-04

申请人： Kaizad R. Mistry ,  Ian R. Post

发明人： Kaizad R. Mistry ,  Ian R. Post

IPC分类号： H01L218236

CPC分类号： H01L21/823807

摘要： A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.

摘要翻译： 一种形成MOS集成电路的方法，其具有至少两种类型的具有不同阈值电压的NFET，并且每种类型具有不同阈值电压的至少两种类型的PFET包括在衬底中形成至少四个有源区域 ，每个区域具有不同的掺杂分布。 修改传统的两个阈值电压CMOS工艺以仅产生一个附加的掩模注入操作来产生四个晶体管阈值电压。 这种额外的注入提高了一种类型MOSFET的阈值电压，同时降低了另一种MOSFET类型的阈值电压。

公开(公告)号：US08426927B2

公开(公告)日：2013-04-23

申请号：US13107783

申请日：2011-05-13

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US07226843B2

公开(公告)日：2007-06-05

申请号：US10261715

申请日：2002-09-30

申请人： Cory E. Weber ,  Gerhard Schrom ,  Ian R. Post ,  Mark A. Stettler

发明人： Cory E. Weber ,  Gerhard Schrom ,  Ian R. Post ,  Mark A. Stettler

IPC分类号： H01L21/336 ,  H01L31/119

CPC分类号： H01L29/1083 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1045

摘要： A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.

摘要翻译： 一种包括形成具有沟道区的晶体管器件的方法; 将第一晕圈注入到通道区域中; 以及将第二不同的光晕注入所述通道区域。 一种包括形成在基板上的栅电极的装置; 形成在栅电极下方的基板和接触点之间的沟道区域; 第一晕轮植入物，其包括所述通道区域中的第一物质; 以及在所述通道区域中包括不同的第二种类的第二晕轮植入物。

公开(公告)号：US06979609B2

公开(公告)日：2005-12-27

申请号：US10426221

申请日：2003-04-30

申请人： Ian R. Post ,  Kaizad Mistry

发明人： Ian R. Post ,  Kaizad Mistry

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/1083 ,  H01L29/6659

摘要： A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.

摘要翻译： 公开了一种在单阈值MOSFET上处理仅需要额外掩模和注入操作的双阈值nMOSFET和pMOSFET的方法。 附加的掩模和注入操作都增强了一种类型的FET的阈值电压掺杂，并补偿了另一种类型的FET的阈值电压掺杂。 当第一阈值电压注入将NMOS器件的阈值电压设置为低阈值电压时，第二阈值电压注入将PMOS器件的阈值电压设置为高阈值电压，第三注入可以增强NMOS器件阈值 植入物以将阈值电压设置为高，同时补偿PMOS器件阈值注入以将阈值电压设置为低。

公开(公告)号：US20130224926A1

公开(公告)日：2013-08-29

申请号：US13857578

申请日：2013-04-05

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

公开(公告)号：US20110215422A1

公开(公告)日：2011-09-08

申请号：US13107783

申请日：2011-05-13

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L21/8238 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US07541239B2

公开(公告)日：2009-06-02

申请号：US11479762

申请日：2006-06-30

申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

IPC分类号： H01L21/8238 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

摘要翻译： 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类别的晶体管的衬底上沉积共形第一沉积层，将沉积层分隔成至少一类晶体管，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

公开(公告)号：US08174060B2

公开(公告)日：2012-05-08

申请号：US13040951

申请日：2011-03-04

申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

IPC分类号： H01L31/119 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.