公开(公告)号：US06614087B1

公开(公告)日：2003-09-02

申请号：US09544290

申请日：2000-04-06

申请人： Kazuhiro Morishita ,  Katsumi Satoh ,  Noritoshi Hirano

发明人： Kazuhiro Morishita ,  Katsumi Satoh ,  Noritoshi Hirano

IPC分类号： H01L3106

CPC分类号： H01L29/868 ,  H01L29/36

摘要： An object is to provide a semiconductor device which is free from such voltage oscillation as may cause malfunction of peripheral equipment. In a semiconductor device having a pin structure, the impurity concentration gradient in an n+ layer (103) serving as a buffer layer is set equal to or less than 2×1018cm−4. Then, when a reverse bias voltage is applied and a depletion layer reaches the n+ layer (103), the expansion of the depletion layer is prevented from rapidly stopping and the voltage oscillation can be suppressed.

摘要翻译： 目的是提供一种半导体器件，该半导体器件没有可能导致外围设备故障的电压振荡。 在具有pin结构的半导体器件中，用作缓冲层的n +层（103）中的杂质浓度梯度被设置为等于或小于2×10 18 cm -4。 然后，当施加反向偏置电压并且耗尽层到达n +层（103）时，消除耗尽层的膨胀被快速停止，并且可以抑制电压振荡。

公开(公告)号：US06479882B2

公开(公告)日：2002-11-12

申请号：US09737962

申请日：2000-12-18

申请人： Yoshihiro Yamaguchi ,  Takeaki Asaeda ,  Katsumi Satoh ,  Noritoshi Hirano

发明人： Yoshihiro Yamaguchi ,  Takeaki Asaeda ,  Katsumi Satoh ,  Noritoshi Hirano

IPC分类号： H01L2900

CPC分类号： H01C7/12 ,  H01L27/0288 ,  H01L29/8605 ,  H01L29/861 ,  H02H9/02

摘要： The current-limiting device 1 includes a silicon substrate 2 having surfaces opposite to each other, and two electrodes 3 deposited respectively on the opposite surfaces of the silicon substrate. The silicon substrate 2 is of a three-layered structure including an N− layer 4 of a low impurity density and an N+ layers 5 of a high impurity density formed respectively on opposite surfaces of the N− layer 4. The electrodes 3, are deposited on an outer surface of each of the N+ layers 5 remote from the N− layer 4. The constant current substantially flows in the current-limiting device 1 if the applied voltage is higher than a predetermined value.

公开(公告)号：US06388276B1

公开(公告)日：2002-05-14

申请号：US09824090

申请日：2001-04-03

申请人： Noritoshi Hirano ,  Yoshihiro Yamaguchi ,  Katsumi Satoh

发明人： Noritoshi Hirano ,  Yoshihiro Yamaguchi ,  Katsumi Satoh

IPC分类号： H01L2974

CPC分类号： H01L29/7416

摘要： Providing a reverse conducting thyristor, wherein a diode and a GTO thyristor are reverse parallel-connected, with which it is possible to reduce a surface area size of a separation portion and avoid variations in insulation characteristics. A separation portion between a diode and a GTO thyristor includes a semiconductor substrate of a first conductivity type, a thin film region of a second conductivity type formed in a major surface of the semiconductor substrate, and a guard ring region of the second conductivity type.

摘要翻译： 提供反向导通晶闸管，其中二极管和GTO晶闸管反向并联，借此可以减小分离部分的表面积尺寸并避免绝缘特性的变化。二极管与GTO之间的分离部分 晶闸管包括形成在半导体衬底的主表面中的第一导电类型的半导体衬底，第二导电类型的薄膜区和第二导电类型的保护环区。

公开(公告)号：US06552413B1

公开(公告)日：2003-04-22

申请号：US09617114

申请日：2000-07-14

申请人： Noritoshi Hirano ,  Katsumi Satoh

发明人： Noritoshi Hirano ,  Katsumi Satoh

IPC分类号： H01L29861

CPC分类号： H01L29/861 ,  Y10S438/979 ,  Y10S438/983

摘要： Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less. Consequently, it is possible to suppress the voltage oscillation without increasing a forward voltage and an energy loss produced during the reverse recovery operation.

摘要翻译： 实施了二极管，其控制在反向恢复操作期间产生的能量损失，并且即使反向偏置电压具有大的值也难以产生施加的电压的振荡。 在诸如硅的半导体衬底中形成N层101和P层102。 此外，阴极侧P层103也形成在N层101上的位于阴极电极105的位置，在施加反向偏置电压期间延伸的耗尽层未达到。 通过设置阴极侧P层103，可以提高在反向恢复操作期间获得的反向电流的电流密度，可以防止二极管的电阻分量的突然变化，并且可以抑制电压振荡的产生。 阴极侧P层103的直径W为约400μm以下，阴极侧P层103的占阴极面的面积的比率保持在大致⅖以下。 因此，可以在不增加正向电压和在反向恢复操作期间产生的能量损失的情况下抑制电压振荡。

公开(公告)号：US06521919B2

公开(公告)日：2003-02-18

申请号：US09813985

申请日：2001-03-22

申请人： Noritoshi Hirano ,  Katsumi Satoh ,  Yoshihiro Yamaguchi

发明人： Noritoshi Hirano ,  Katsumi Satoh ,  Yoshihiro Yamaguchi

IPC分类号： H01L2974

CPC分类号： H01L29/66363 ,  H01L23/051 ,  H01L29/744 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is composed a semiconductor substrate having a first conducting-type first semiconductor layer, a second conducting-type second semiconductor layer, a first conducting-type third semiconductor layer, a second conducting-type fourth semiconductor layer and a first conducting-type fifth semiconductor layer, a first main electrode for short-circuiting the first semiconductor layer and the second semiconductor layer, a second main electrode for short-circuiting the fourth semiconductor layer and the fifth semiconductor layer, and a control electrode provided on the third semiconductor layer. The first semiconductor layer and the second semiconductor layer form a joint. The second semiconductor layer and the third semiconductor layer form a joint. The third semiconductor layer and the fourth semiconductor layer form a joint. The fourth semiconductor layer and the fifth semiconductor layer form a joint.

摘要翻译： 半导体器件由具有第一导电型第一半导体层，第二导电型第二半导体层，第一导电型第三半导体层，第二导电型第四半导体层和第一导电型第二半导体层 第五半导体层，用于使第一半导体层和第二半导体层短路的第一主电极，用于使第四半导体层和第五半导体层短路的第二主电极，以及设置在第三半导体层上的控制电极 。 第一半导体层和第二半导体层形成接头。 第二半导体层和第三半导体层形成接头。 第三半导体层和第四半导体层形成接头。 第四半导体层和第五半导体层形成接头。

公开(公告)号：US06489666B1

公开(公告)日：2002-12-03

申请号：US09624998

申请日：2000-07-25

申请人： Yoshihiro Yamaguchi ,  Katsumi Satoh ,  Noritoshi Hirano

发明人： Yoshihiro Yamaguchi ,  Katsumi Satoh ,  Noritoshi Hirano

IPC分类号： H01L2906

CPC分类号： H01L29/861 ,  H01L29/0661

摘要： A semiconductor device (102) comprises an N type semiconductor substrate (1). A P layer (22) is formed in a first surface (S1) of the semiconductor substrate (1), and a P layer (23) is formed in the semiconductor substrate (1) and in contact with the first surface (S1) and a second surface (S2) of the semiconductor substrate (1) corresponding to a beveled surface. The P layer (23) surrounds the P layer (22) in non-contacting relationship with the P layer (22). A separation distance (D) between the P layers (22, 23) is set at not greater than 50 &mgr;m. A distance (D23) between a third surface (S3) of the semiconductor substrate (1) and a portion of the P layer (23) which is closer to the third surface (S3) is less than a distance (D22) between the third surface (S3) and a portion of the P layer (22) which is closer to the third surface (S3). An N++ layer (24) is formed in part of the third surface (S3) which is substantially opposed to the P layer (22), and an N+ layer (25) is formed in contact with the N++ layer (24) and the third surface (S3). A cathode electrode (33) is formed on the third surface (S3) so as to cover a region (S322) of the third surface (S3) which is opposed to the P layer (22). The semiconductor device (102) suppresses heat generation to perform a stable operation.

摘要翻译： 半导体器件（102）包括N型半导体衬底（1）。 AP层（22）形成在半导体衬底（1）的第一表面（S1）中，并且在半导体衬底（1）中形成P层（23）并与第一表面（S1）接触，并且 所述半导体衬底（1）的第二表面（S2）对应于斜面。 P层（23）以与P层（22）非接触的关系围绕P层（22）。 P层（22,23）之间的间隔距离（D）设定为50μm以下。 半导体衬底（1）的第三表面（S3）与更靠近第三表面（S3）的P层（23）的一部分之间的距离（D23）小于第三 表面（S3）和更靠近第三表面（S3）的P层（22）的一部分。 在基本上与P层（22）相对的第三表面（S3）的一部分中形成N ++层（24），并且形成与N ++层（24）接触的N +层（25） 表面（S3）。 在第三表面（S3）上形成阴极电极（33），以覆盖与P层（22）相对的第三表面（S3）的区域（S322）。 半导体装置（102）抑制发热来进行稳定的动作。

公开(公告)号：US06388306B1

公开(公告)日：2002-05-14

申请号：US09619316

申请日：2000-07-18

申请人： Noritoshi Hirano ,  Katsumi Satoh

发明人： Noritoshi Hirano ,  Katsumi Satoh

IPC分类号： H01L2900

CPC分类号： H01L29/87 ,  H01L29/861

摘要： An object is to obtain a semiconductor device having a PN junction which can suppress voltage oscillation without exerting any adverse effects. The film thickness of the N− layer (101) is set to satisfy both of a first condition that the depletion layer extending in the N− layer (101) from the PN junction between the N− layer (101) and the P layer (102) does not reach the N+ layer (103) when a reverse voltage of about ½ to ⅔ of the voltage blocking capability of the diode is applied and a second condition that the depletion layer reaches the N+ layer (103) when a reverse voltage exceeding about ⅔ of the voltage blocking capability is applied. Further, the impurity concentration (specific resistance) of the N− layer (101) is set so that the electric field which acts on the depletion layer when the reverse bias voltage is set equivalent to the voltage blocking capability does not exceed the maximum field strength of silicon.

摘要翻译： 目的是获得具有PN结的半导体器件，其可以抑制电压振荡而不产生任何不利影响。 N层（101）的膜厚被设定为满足从N层（101）和P层（N层）的PN结延伸的N层（101）中的耗尽层的第一条件 102）当施加二极管的电压阻断能力的约1/2的反向电压时，N +层（103）不到达N +层（103），当反向电压超过第二条件时，耗尽层到达N +层（103） 大约应用了电压阻塞能力。 此外，设定N层（101）的杂质浓度（电阻率），使得当反偏压设定为等于电压阻断能力时作用在耗尽层上的电场不会超过最大场强 的硅。

公开(公告)号：US06657239B1

公开(公告)日：2003-12-02

申请号：US09784451

申请日：2001-02-27

申请人： Kazuhiro Morishita ,  Katsumi Satoh

发明人： Kazuhiro Morishita ,  Katsumi Satoh

IPC分类号： H01L2945

CPC分类号： H01L29/41716 ,  H01L29/42308

摘要： In order to reduce a turn-on time of a power switching semiconductor device at a low cost, a first main electrode divided into a plurality of segments forming segment rows of a multi-concentric circle and a control electrode surrounding the segments are formed on a front major surface of a semiconductor substrate, and a second electrode is formed on a rear major surface thereof, and a turn-on operation is performed between the first main electrode and the second main electrode with a control signal inputted from the control electrode, specifying a relationship between a width of a segment and a distance between adjacent segments, and others.

摘要翻译： 为了以低成本降低功率开关半导体器件的导通时间，分割成形成多同心圆的段行的多个段的第一主电极和围绕该段的控制电极形成在 半导体衬底的前主表面和第二电极形成在其后主表面上，并且利用从控制电极输入的控制信号在第一主电极和第二主电极之间进行导通操作，指定 片段的宽度与相邻片段之间的距离之间的关系等。

公开(公告)号：US06521918B2

公开(公告)日：2003-02-18

申请号：US09566738

申请日：2000-05-09

申请人： Kenji Oota ,  Kazuhiro Morishita ,  Katsumi Satoh

发明人： Kenji Oota ,  Kazuhiro Morishita ,  Katsumi Satoh

IPC分类号： H01L31111

CPC分类号： H01L29/0692 ,  H01L29/742 ,  H01L29/744

摘要： To make it possible to control turn-off operation even after switch over to transistor operation after commutation of the main current from cathode electrode to gate electrode in turn-off operation, a semiconductor device according to the invention comprises a first electrode, a first region of first conduction type provided on the first electrode, a second region of second conduction type provided on the first region, a third region and a fourth region of first conduction type respectively provided on the second region with a predetermined distance from each other to allow formation of a channel region on the second region, a fifth region of second conduction type provided on the third region, a second electrode provided on the fifth region, a gate electrode established in contact with the fourth region and a control electrode provided on a separate region between the third and fourth regions on the second region to control the channel region through an insulation layer.

公开(公告)号：US06218683B1

公开(公告)日：2001-04-17

申请号：US09463407

申请日：2000-02-01

申请人： Shinji Koga ,  Kazuhiro Morishita ,  Katsumi Satoh

发明人： Shinji Koga ,  Kazuhiro Morishita ,  Katsumi Satoh

IPC分类号： H01L2974

CPC分类号： H01L29/32 ,  H01L29/861 ,  H01L29/868

摘要： The present invention relates to a diode, and has an object to simultaneously implement a high di/dt capability, a low reverse recovery loss and a low forward voltage and to suppress generation of voltage oscillation. In order to achieve the above-mentioned object, life time killers are selectively introduced into a semiconductor substrate (20) comprising a P layer (1), an N− layer (21) and an N+ layer (3). A density of the introduced life time killers is the highest in a first region (6) adjacent to the P layer (1), and is the second highest in a second region (7) in the N− layer (21). The life time killers are not introduced into a third region (2). Accordingly, a life time in the N− layer (21) is expressed by the first region (6)

摘要翻译： 本发明涉及一种二极管，其目的在于同时实现高di / dt能力，低反向恢复损耗和低正向电压，并抑制电压振荡的产生。 为了实现上述目的，将寿命杀手选择性地引入到包括P层（1），N层（21）和N +层（3）的半导体衬底（20）中。 引入的寿命杀伤剂的密度在与P层（1）相邻的第一区域（6）中是最高的，并且是N层（21）中的第二区域（7）中的第二高度。 生命时代的杀手并没有被引入第三个地区（2）。 因此，通过第一区域（6）<第二区域（7）<第三区域（2）表示N层（21）中的寿命。 第二区域（7）和第三区域（2）与P层（1）相邻。 此外，第二区域（7）环绕第三区域（2）。