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公开(公告)号：US20110133797A1
公开(公告)日：2011-06-09
申请号：US13028049
申请日：2011-02-15
申请人： Kartik M. Sridharan
发明人： Kartik M. Sridharan
IPC分类号： H03L7/06
摘要： A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).
摘要翻译： 数字频率合成器可以采用单源设计，多路复用器设计，分数分频器设计或倍频器和分频器设计来实现。 实现可以利用控制器抖动电路或Δ-Σ调制器。 频率合成器可以以CMOS结构实现，并且可以利用清理锁相环（PLL）。
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2.发明授权Method and system for directly modulating a voltage controlled oscillator for use in frequency/phase modulated systems 失效用于频率/相位调制系统中直接调制压控振荡器的方法和系统公开(公告)号：US06549078B1
公开(公告)日：2003-04-15
申请号：US09715632
申请日：2000-11-18
IPC分类号： H03L708
CPC分类号： H03C3/0991 , H03C3/0925 , H03C3/0941 , H03C3/095 , H03L7/18 , H03L2207/06 , Y10S331/02
摘要： A method for generating a plurality of frequencies having predetermined frequency deviations from a phase lock loop device including a VCO having a main voltage input, a modulation voltage input and a frequency output, a first and second feedback loop digital divider, each having an input and an output, a phase frequency detector having a first and second input and an output, a reference frequency generator such as a crystal oscillator having an output, a first and second reference frequency digital divider, each having an input and an output, a loop filter having an input and an output, a switch having an input and a first and a second switched output, a hold circuit having an input and an output, a memory circuit for storing the a lock voltage and the corresponding loop output frequency, the steps including; setting a first initial predetermined value of the first feedback loop digital divider, connecting a switch output to the main input of the VCO, supplying a first predetermined reference frequency to the phase frequency divider, supplying a loop correction voltage Vr, to a main drive input of a VCO, allowing the phase lock loop to lock, switching the switch output to the modulation input of the VCO, changing the initial predetermined value of the first feedback loop digital divider, supplying a second loop correction voltage Vj, allowing the phase lock loop to lock, storing the new lock voltage in a memory circuit.
摘要翻译： 一种用于产生具有预定频率偏移的多个频率的方法，所述多个频率具有包括具有主电压输入的VCO，调制电压输入和频率输出的第一和第二反馈回路数字除法器的锁相环装置，每个具有输入和 输出，具有第一和第二输入和输出的相位频率检测器，诸如具有输出的晶体振荡器的参考频率发生器，具有输入和输出的第一和第二参考频率数字分频器，环路滤波器 具有输入和输出的开关，具有输入和第一和第二开关输出的开关，具有输入和输出的保持电路，用于存储锁定电压和相应的环路输出频率的存储电路，所述步骤包括 ; 设置第一反馈环数字分频器的第一初始预定值，将开关输出连接到VCO的主输入端，向相位分频器提供第一预定参考频率，向环路校正电压Vr提供环路校正电压Vr 的VCO，允许锁相环锁定，将开关输出切换到VCO的调制输入，改变第一反馈环数字分频器的初始预定值，提供第二环路校正电压Vj，允许锁相环 锁定，将新的锁定电压存储在存储器电路中。
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公开(公告)号：US20090146747A1
公开(公告)日：2009-06-11
申请号：US12334359
申请日：2008-12-12
申请人： Kartik M. Sridharan
发明人： Kartik M. Sridharan
IPC分类号： H03L7/16
摘要： A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).
摘要翻译： 数字频率合成器可以采用单源设计，多路复用器设计，分数分频器设计或倍频器和分频器设计来实现。 实现可以利用控制器抖动电路或Δ-Σ调制器。 频率合成器可以以CMOS结构实现，并且可以利用清理锁相环（PLL）。
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公开(公告)号：US07151011B2
公开(公告)日：2006-12-19
申请号：US10243487
申请日：2002-09-13
IPC分类号： H01L21/56
CPC分类号： H01L23/60 , H01L23/49816 , H01L23/5227 , H01L23/552 , H01L23/585 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H01L2924/3025 , H01L2224/0401
摘要： A package for housing a device (e.g., an integrated circuit chip or die) includes a Faraday cage. The Faraday cage is at least partially formed in the integrated circuit die. The die includes conductive vias and solder balls surrounding a circuit. The package can be a ball grid array (BGA) package or flip chip package. The package substrate can include a ground plane.
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公开(公告)号：US06937668B2
公开(公告)日：2005-08-30
申请号：US09819789
申请日：2001-03-28
IPC分类号： H04L27/02 , H03F3/24 , H04L27/10 , H04L27/18 , H04L27/32 , H04L27/36 , H04K1/02 , H04L25/03 , H04L25/49
CPC分类号： H03F3/24 , H04L27/361
摘要： A modulator and a method of modulating utilizes phase or frequency modulation and amplitude modulation. A delay circuit or synchronization circuit is utilized to coordinate the performance of amplitude modulation and phase modulation. The amplitude modulation can be provided after phase modulation is provided to the signal. The modulation circuit can be utilized in any frequency range including high frequency and low frequency circuits.
摘要翻译： 调制器和调制方法利用相位或频率调制和幅度调制。 利用延迟电路或同步电路协调幅度调制和相位调制的性能。 可以在向信号提供相位调制之后提供幅度调制。 调制电路可以在包括高频和低频电路的任何频率范围内使用。
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公开(公告)号：US06486534B1
公开(公告)日：2002-11-26
申请号：US09785620
申请日：2001-02-16
IPC分类号： H01L2360
CPC分类号： H01L23/60 , H01L23/49816 , H01L23/5227 , H01L23/552 , H01L23/585 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H01L2924/3025 , H01L2224/0401
摘要： A package for housing a device (e.g., an integrated circuit chip or die) includes a Faraday cage. The Faraday cage is at least partially formed in the integrated circuit die. The die includes conductive vias and solder balls surrounding a circuit. The package can be a ball grid array (BGA) package or flip chip package. The package substrate can include a ground plane.
摘要翻译： 用于容纳器件（例如，集成电路芯片或裸片）的封装包括法拉第笼。 法拉第笼子至少部分地形成在集成电路管芯中。 芯片包括导电通孔和围绕电路的焊球。 封装可以是球栅阵列（BGA）封装或倒装芯片封装。 封装衬底可以包括接地平面。
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公开(公告)号：US07898345B2
公开(公告)日：2011-03-01
申请号：US12334359
申请日：2008-12-12
申请人： Kartik M. Sridharan
发明人： Kartik M. Sridharan
IPC分类号： H03B21/00
摘要： A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).
摘要翻译： 数字频率合成器可以采用单源设计，多路复用器设计，分数分频器设计或倍频器和分频器设计来实现。 实现可以利用控制器抖动电路或Δ-Σ调制器。 频率合成器可以以CMOS结构实现，并且可以利用清理锁相环（PLL）。
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公开(公告)号：US07482885B2
公开(公告)日：2009-01-27
申请号：US11321110
申请日：2005-12-29
申请人： Kartik M. Sridharan
发明人： Kartik M. Sridharan
摘要： A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).
摘要翻译： 数字频率合成器可以采用单源设计，多路复用器设计，分数分频器设计或倍频器和分频器设计来实现。 实现可以利用控制器抖动电路或Δ-Σ调制器。 频率合成器可以以CMOS结构实现，并且可以利用清理锁相环（PLL）。
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9.发明授权公开(公告)号：US06831911B1
公开(公告)日：2004-12-14
申请号：US09715502
申请日：2000-11-18
IPC分类号： H04S300
摘要： A system and method for processing signals from at least two sources, using a receiver having a timer and a local code sequence, the method comprising, providing at least one signal channel divided into a plurality of sequential time slots processing said signal from a first of said two sources in a first time slot of the plurality of time slots to provide a first time slot signal, processing said signal from a second of said two sources in a second time slot of the plurality of time slots to provide a second time slot signal, processing said signal from said first of said two sources in a third time slot of the plurality of time slots to provide a third time slot signal, said first, second and third time slots occurring in sequential order, comparing said local code sequence to said signals in said first and third time slots by incrementing the local code sequence during the interval between said first and third time slots.
摘要翻译： 一种用于使用具有定时器和本地码序列的接收机处理来自至少两个源的信号的系统和方法，所述方法包括：提供分割成多个连续时隙的至少一个信号信道，所述多个连续时隙处理来自 在多个时隙的第一时隙中表示两个源以提供第一时隙信号，在多个时隙中的第二时隙中处理来自所述两个源中的第二个的所述信号，以提供第二时隙信号 在所述多个时隙的第三时隙中从所述两个源中的所述第一个源处理所述信号以提供第三时隙信号，所述第一，第二和第三时隙按顺序发生，将所述本地码序列与所述 通过在所述第一和第三时隙之间的间隔期间递增本地码序列来在所述第一和第三时隙中的信号。
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