公开(公告)号：US20240388300A1

公开(公告)日：2024-11-21

申请号：US18496244

申请日：2023-10-27

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Changyeop LEE ,  Seung-Tak RYU ,  Junho CHEON

IPC: H03M1/00

Abstract: A voltage-to-time converter (VTC) circuit includes an input capacitor being charged according to an input voltage during a precharge operation; an output capacitor being charged during the precharge operation; a first transistor configured to discharge the output capacitor according to a voltage charged in the input capacitor during a first operation following the precharge operation; and a second transistor configured to charge the output capacitor according to the voltage charged in the input capacitor during a second operation following the first operation.

公开(公告)号：US20190222220A1

公开(公告)日：2019-07-18

申请号：US16194824

申请日：2018-11-19

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seung-Tak RYU ,  Dongjin CHANG

IPC: H03M1/10 ,  H03M1/08

Abstract: An electronic circuit includes a reference ADC, a delay circuit, and a main ADC. The reference ADC converts an input signal to an upper bit string of output data, in response to a reference clock. The delay circuit delays a source clock by a delay time to output a main clock. The main ADC converts the input signal to a lower bit string of the output data, in response to the main clock. When a value of the most significant bit included in the lower bit string is identical to a value of the bit which is adjacent to the most significant bit and lower than the most significant bit, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the most significant bit of the lower bit string.

公开(公告)号：US20200274543A1

公开(公告)日：2020-08-27

申请号：US16798716

申请日：2020-02-24

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seung-Tak RYU ,  Minjae Seo

IPC: H03M1/00

Abstract: An electronic circuit includes a first converting circuit, an amplifying circuit, and a second converting circuit. The first converting circuit outputs a first residual voltage associated with converting an analog signal into a first digital signal and a second residual voltage generated based on the first residual voltage. The amplifying circuit generates a third residual voltage by amplifying the first residual voltage through an amplifying path during a first time duration and generates a fourth residual voltage by amplifying the second residual voltage through the amplifying path during a second time duration after the first time duration. The second converting circuit generates a second digital signal associated with the analog signal by performing an interpolation operation based on the third residual voltage and the fourth residual voltage.

公开(公告)号：US20190173480A1

公开(公告)日：2019-06-06

申请号：US16194878

申请日：2018-11-19

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seung-Tak RYU ,  Yiju ROH

IPC: H03M1/10 ,  H03K5/135 ,  H03K5/1534 ,  H03M1/08

Abstract: An electronic circuit includes a reference ADC and a plurality of sub-ADCs. The reference ADC converts an input signal to reference data in response to a reference clock. The plurality of sub-ADCs may respectively convert the input signal to a plurality of output data, in response respectively to the plurality of conversion clocks providing different timings. Based on a difference between the reference data and each of the plurality of output data and output data corresponding to the difference among the plurality of output data, a timing of a conversion clock associated with the output data corresponding to the difference among the plurality of conversion clocks is adjusted.