公开(公告)号：US20190173480A1

公开(公告)日：2019-06-06

申请号：US16194878

申请日：2018-11-19

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seung-Tak RYU ,  Yiju ROH

IPC: H03M1/10 ,  H03K5/135 ,  H03K5/1534 ,  H03M1/08

Abstract: An electronic circuit includes a reference ADC and a plurality of sub-ADCs. The reference ADC converts an input signal to reference data in response to a reference clock. The plurality of sub-ADCs may respectively convert the input signal to a plurality of output data, in response respectively to the plurality of conversion clocks providing different timings. Based on a difference between the reference data and each of the plurality of output data and output data corresponding to the difference among the plurality of output data, a timing of a conversion clock associated with the output data corresponding to the difference among the plurality of conversion clocks is adjusted.