公开(公告)号：US08280559B2

公开(公告)日：2012-10-02

申请号：US12137436

申请日：2008-06-11

申请人： Jeffrey Herman ,  Sagheer Ahmad

发明人： Jeffrey Herman ,  Sagheer Ahmad

IPC分类号： G05D23/00

CPC分类号： G05D23/19

摘要： In an embodiment, an integrated circuit includes an input configured to receive a first control signal and an output module configured to generate an output signal based at least on the first control signal and a second control signal generated based at least on a measured temperature of the IC. The output signal is configured to control a cooling device.

摘要翻译： 在一个实施例中，集成电路包括被配置为接收第一控制信号的输入和被配置为至少基于第一控制信号产生输出信号的输出模块，以及基于至少基于第一控制信号的测量温度生成的第二控制信号 我知道了。 输出信号被配置为控制冷却装置。

公开(公告)号：US09104423B2

公开(公告)日：2015-08-11

申请号：US13473042

申请日：2012-05-16

申请人： Sagheer Ahmad ,  Jay Kishora Gupta ,  Laurent Rene Moll

发明人： Sagheer Ahmad ,  Jay Kishora Gupta ,  Laurent Rene Moll

IPC分类号： G06F1/32 ,  G06F9/44

CPC分类号： G06F1/329 ,  G06F1/3209 ,  G06F9/4418 ,  Y02D10/24

摘要： A system and method for power management by providing advance notice of events. The method includes snooping a register of an operating system timer to determine a timer period associated with a scheduled event. A unit of a computer system is identified that is in a low power state. A wake up latency of the unit is determined that is based on the low power state. An advance period is determined based on the wake up latency. An advance notice of the operating system timer is triggered based on the timer period and the advance period to wake up the unit.

摘要翻译： 提供事件通知的电源管理系统和方法。 该方法包括窥探操作系统定时器的寄存器以确定与调度事件相关联的定时器周期。 识别出处于低功率状态的计算机系统的单元。 确定基于低功率状态的单元的唤醒延迟。 基于唤醒延迟确定提前期。 基于定时器周期和唤醒单元的提前周期触发操作系统定时器的提前通知。

公开(公告)号：US20130311797A1

公开(公告)日：2013-11-21

申请号：US13473042

申请日：2012-05-16

申请人： Sagheer Ahmad ,  Jay Kishora Gupta ,  Laurent Rene Moll

发明人： Sagheer Ahmad ,  Jay Kishora Gupta ,  Laurent Rene Moll

IPC分类号： G06F1/26

CPC分类号： G06F1/329 ,  G06F1/3209 ,  G06F9/4418 ,  Y02D10/24

摘要： A system and method for power management by providing advance notice of events. The method includes snooping a register of an operating system timer to determine a timer period associated with a scheduled event. A unit of a computer system is identified that is in a low power state. A wake up latency of the unit is determined that is based on the low power state. An advance period is determined based on the wake up latency. An advance notice of the operating system timer is triggered based on the timer period and the advance period to wake up the unit.

摘要翻译： 提供事件通知的电源管理系统和方法。 该方法包括窥探操作系统定时器的寄存器以确定与调度事件相关联的定时器周期。 识别出处于低功率状态的计算机系统的单元。 确定基于低功率状态的单元的唤醒延迟。 基于唤醒延迟确定提前期。 基于定时器周期和唤醒单元的提前周期触发操作系统定时器的提前通知。

公开(公告)号：US09471395B2

公开(公告)日：2016-10-18

申请号：US13592748

申请日：2012-08-23

申请人： Sagheer Ahmad ,  Shailender Chaudhry ,  John George Mathieson ,  Mark Alan Overby

发明人： Sagheer Ahmad ,  Shailender Chaudhry ,  John George Mathieson ,  Mark Alan Overby

IPC分类号： G06F9/46 ,  G06F9/50

CPC分类号： G06F9/5094 ,  G06F9/5088 ,  G06F2209/5019 ,  G06F2209/5022 ,  Y02D10/22 ,  Y02D10/32

摘要： Embodiments of the present technology provide for migrating processes executing one any one of a plurality of cores in a multi-core cluster to a core of a separate cluster without first having to transfer the processes to a predetermined core of the multi-core cluster. Similarly, the processes may be transferred from the core of the separate cluster to the given core of the multi-core cluster.

摘要翻译： 本技术的实施例提供了将多核心集群中的多个核心中的任一个执行到单独集群的核心的迁移过程，而不必先将流程转移到多核集群的预定核心。 类似地，这些过程可以从单独集群的核心转移到多核集群的给定核心。

公开(公告)号：US20130198549A1

公开(公告)日：2013-08-01

申请号：US13360559

申请日：2012-01-27

申请人： Matthew Raymond LONGNECKER ,  Scott Alan Williams ,  Sagheer Ahmad ,  Robert Alan Bignell ,  Venkata Krishna Reddy Dumpa

发明人： Matthew Raymond LONGNECKER ,  Scott Alan Williams ,  Sagheer Ahmad ,  Robert Alan Bignell ,  Venkata Krishna Reddy Dumpa

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3206 ,  G06F9/327 ,  Y02D10/128

摘要： To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core.

摘要翻译： 为了保持功率并提高CPU的整体效率，平台空闲驱动器使电源门控制器切断到空闲核心的电源。 这种电源门控是自主的，即操作系统和其他核心不涉及。 在运行中，平台空闲驱动器首先准备核心和电源门控制器，用于电源门控。 平台空闲驱动程序然后触发电源门控。 电源门控制器监视中断控制器释放的中断，如果释放的中断中的任何一个与电源门控核心相关联，则电源门控制器将恢复分配给核心的电源。

公开(公告)号：US08099638B2

公开(公告)日：2012-01-17

申请号：US10987499

申请日：2004-11-12

申请人： Sagheer Ahmad ,  Eric Scott ,  Joe Macri ,  Dan Shimizu

发明人： Sagheer Ahmad ,  Eric Scott ,  Joe Macri ,  Dan Shimizu

IPC分类号： G11C29/12 ,  G06F12/00

CPC分类号： G11C29/36 ,  G11C29/10 ,  G11C2029/3602

摘要： The disclosure relates to a programmable virtual memory client, that includes programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns. Additionally, the virtual memory client includes virtual memory client control logic configured to use the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

摘要翻译： 本公开涉及可编程虚拟存储器客户端，其包括被配置为从多个存储的数据模式生成至少一个数据模式序列的可编程控制逻辑。 另外，虚拟存储器客户端包括虚拟存储器客户端控制逻辑，其被配置为将所生成的至少一个数据模式序列用于从至少一个存储器设备的读取和写入中的至少一个。 一种方法包括从多个存储的数据模式生成至少一个数据模式序列，并从存储器设备写入和读取数据模式序列。

公开(公告)号：US07222251B2

公开(公告)日：2007-05-22

申请号：US10358181

申请日：2003-02-05

申请人： Sagheer Ahmad ,  Erik Norden ,  Rob Ober

发明人： Sagheer Ahmad ,  Erik Norden ,  Rob Ober

IPC分类号： G06H13/24

CPC分类号： G06F9/3867 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D50/20

摘要： An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

摘要翻译： 空闲模式系统具有时钟门控电路，总线接口单元，存储器接口以及中断和空闲控制单元。 时钟选通电路接收第一时钟和指定的空闲确认信号。 当接收到少于所有指定的空闲确认信号时，时钟选通电路基于第一时钟信号产生第二时钟信号。 当接收到所有指定的空闲确认信号时，时钟选通电路不产生第二时钟信号。 总线接口单元接收总线访问请求并接收第一和第二时钟信号。 当总线访问请求被发出时，总线接口单元取消断言其空闲确认信号并传递总线访问请求。 存储器接口在第二个时钟上工作。 一个接口从总线接口单元接收总线访问请求，撤销其空闲确认信号，处理总线访问请求，并在完成后重新确认其空闲确认信号。

公开(公告)号：US08949645B2

公开(公告)日：2015-02-03

申请号：US13357352

申请日：2012-01-24

申请人： Sagheer Ahmad ,  Tezaswi Raja

发明人： Sagheer Ahmad ,  Tezaswi Raja

IPC分类号： G06F1/26 ,  G06F1/18

CPC分类号： G06F1/189 ,  G06F1/3243 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/152 ,  Y02D10/171

摘要： Embodiments related to controlling power distribution within a microprocessor are provided. In one example, a microprocessor comprising a power supply is provided. The example microprocessor also includes a plurality of power gate zones configured to receive power from the power supply, each power gate zone including a plurality of power gates, where the power gates within any given one of the power gate zones are controlled by the microprocessor independently of its control of power gates within any other of the power gate zones. The example microprocessor is operative to cause power initially to be supplied to a first power gate in a first one of the power gate zones, power then to be supplied to a second power gate in a second one of the power gate zones, and power then to be supplied to a third power gate in the first one of the power gate zones.

摘要翻译： 提供了关于控制微处理器内的配电的实施例。 在一个示例中，提供了包括电源的微处理器。 示例性微处理器还包括多个电源栅区，其被配置为从电源接收电力，每个电源栅区包括多个功率门，其中任何给定的一个功率门区内的功率门由微处理器独立地控制 控制任何其他电源门区内的电源门。 该示例性微处理器可操作以最初将功率提供给第一个功率门区域中的第一功率门，然后供电到第二个功率门区域中的第二功率门，然后电源 被供应到第一个功率门区中的第三电源门。

公开(公告)号：US20140032947A1

公开(公告)日：2014-01-30

申请号：US13561884

申请日：2012-07-30

申请人： Sagheer Ahmad ,  Edward L. Riegelsberger ,  Tony Yuhsiang Cheng ,  Laurent Rene Moll ,  Brian Keith Langendorf

发明人： Sagheer Ahmad ,  Edward L. Riegelsberger ,  Tony Yuhsiang Cheng ,  Laurent Rene Moll ,  Brian Keith Langendorf

IPC分类号： G06F1/00

CPC分类号： G06F1/3275 ,  G06F9/4418 ,  Y02D10/14 ,  Y02D50/20

摘要： A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.

摘要翻译： 一种用于管理存储器控制器的方法，包括从多个低功率状态中选择低功率状态。 该方法还包括：当转换完成时，转换到低功率并进入低功率状态，只要没有接收到唤醒事件。 一种装置包括：控制器，被配置为选择用于转换的功率状态;状态机，被配置为执行用于通过总线连接到存储器的存储器控​​制器的功率状态之间的转换的步骤;被配置为存储至少一个上下文的存储器;以及 上下文引擎，被配置为在所述状态机引擎的方向上将所述至少一个上下文流向所述存储器控制器。 流式传输包括将上下文数据的N个部分作为流传送到存储器控制器中的N个寄存器。 上下文包括对应于选择用于转换的状态的多个校准。

公开(公告)号：US07149926B2

公开(公告)日：2006-12-12

申请号：US10444918

申请日：2003-05-22

申请人： Sagheer Ahmad ,  Robert E. Ober

发明人： Sagheer Ahmad ,  Robert E. Ober

IPC分类号： G06F11/00

CPC分类号： G06F11/364 ,  G06F11/3656

摘要： An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output buffer, and selectively controls the rate at which the trace information is output from the output buffer to an off-chip debug system. A configurable on-chip filter circuit selectively passes data and program information based on a wide range of user-defined combinations and/or sequences of trigger events (e.g., instruction addresses/types or data addresses/values). The filtered trace information is then compressed using separate data and program compression circuits, and passed to separate data and program output buffer. The data output buffer includes an adjustable read (output) rate (e.g., one-half or one-quarter of the processor core clock cycle), and allows a user to select between one or two output pointers.

摘要翻译： 具有可编程跟踪端口的嵌入式处理器，其选择性地限制从处理器核心传递到输出缓冲器的跟踪信息量，并且选择性地控制跟踪信息从输出缓冲器输出到片外调试系统的速率。 可配置片上滤波器电路基于用户定义的组合和/或触发事件序列（例如，指令地址/类型或数据地址/值）的大范围选择性地传送数据和程序信息。 然后，使用单独的数据和程序压缩电路压缩过滤的跟踪信息，并将其传递给单独的数据和程序输出缓冲区。 数据输出缓冲器包括可调读取（输出）速率（例如，处理器核心时钟周期的一半或四分之一），并且允许用户在一个或两个输出指针之间进行选择。