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公开(公告)号：US20230036779A1
公开(公告)日：2023-02-02
申请号：US17961617
申请日：2022-10-07
Inventor： Hideo TANABE , Masaru TAKABATAKE , Toshiki KANEKO , Atsushi HASEGAWA , Hiroko SEHATA
IPC: G02F1/1333 , G02F1/1362 , G02F1/1368 , H01L27/12 , H01L29/786
Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
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公开(公告)号：US20210181569A1
公开(公告)日：2021-06-17
申请号：US17187945
申请日：2021-03-01
Inventor： Hideo TANABE , Masaru TAKABATAKE , Toshiki KANEKO , Atsushi HASEGAWA , Hiroko SEHATA
IPC: G02F1/1333 , G02F1/1362 , G02F1/1368 , H01L27/12 , H01L29/786
Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
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公开(公告)号：US20190156905A1
公开(公告)日：2019-05-23
申请号：US16238771
申请日：2019-01-03
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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4.发明申请公开(公告)号：US20140340293A1
公开(公告)日：2014-11-20
申请号：US14449363
申请日：2014-08-01
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
Abstract translation: 一种包括双向移位寄存器电路的显示装置，包括：多个级联连接的寄存器电路; 各种电路，用于响应于输入到各种终端的各种信号将各种节点设置到各种电压电平; 以及输出电路，其在第一节点的电压为高电平时输出时钟脉冲作为输出脉冲，其中，在正向移位操作时，底部伪寄存器电路未输入复位信号和底部的第一节点 如果底部伪寄存器电路的初始复位电路接收到反向触发信号，则虚拟寄存器电路被复位，并且其中，在反向移位操作时，顶部伪寄存器电路不输入复位信号和顶部伪随机的第一个节点 如果顶部伪寄存器电路的初始复位电路接收到正向触发信号，则寄存器电路复位。
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公开(公告)号：US20200321068A1
公开(公告)日：2020-10-08
申请号：US16906286
申请日：2020-06-19
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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Patent Agency Ranking
公开(公告)号：US20200150484A1
公开(公告)日：2020-05-14
申请号：US16735388
申请日：2020-01-06
Inventor： Hideo TANABE , Masaru TAKABATAKE , Toshiki KANEKO , Atsushi HASEGAWA , Hiroko SEHATA
IPC: G02F1/1333 , G02F1/1362 , G02F1/1368 , H01L27/12 , H01L29/786
Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
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公开(公告)号：US20180114584A1
公开(公告)日：2018-04-26
申请号：US15848052
申请日：2017-12-20
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US20160147110A1
公开(公告)日：2016-05-26
申请号：US15002453
申请日：2016-01-21
Inventor： Hideo TANABE , Masaru TAKABATAKE , Toshiki KANEKO , Atsushi HASEGAWA , Hiroko SEHATA
IPC: G02F1/1333
CPC classification number: G02F1/133345 , G02F1/133305 , G02F1/133504 , G02F1/133555 , G02F1/134363 , G02F1/136213 , G02F1/136227 , G02F1/1368 , G02F2001/13685 , H01L27/124 , H01L27/1248 , H01L29/78675
Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
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9.发明申请公开(公告)号：US20150270012A1
公开(公告)日：2015-09-24
申请号：US14729238
申请日：2015-06-03
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
Abstract translation: 一种包括双向移位寄存器电路的显示装置，包括：多个级联连接的寄存器电路; 各种电路，用于响应于输入到各种终端的各种信号将各种节点设置到各种电压电平; 以及输出电路，其在第一节点的电压为高电平时输出时钟脉冲作为输出脉冲，其中，在正向移位操作时，底部伪寄存器电路未输入复位信号和底部的第一节点 如果底部伪寄存器电路的初始复位电路接收到反向触发信号，则虚拟寄存器电路被复位，并且其中，在反向移位操作时，顶部伪寄存器电路不输入复位信号和顶部伪器件的第一个节点 如果顶部伪寄存器电路的初始复位电路接收到正向触发信号，则寄存器电路复位。
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10.发明申请公开(公告)号：US20140340294A1
公开(公告)日：2014-11-20
申请号：US14449348
申请日：2014-08-01
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3674 , G09G2310/0286 , G09G2310/066 , G09G2330/025 , G11C19/184 , G11C19/28
Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.
Abstract translation: 一种显示装置，包括用于输出各种脉冲和触发的各种部分，电路和其它装置，用于控制前向移位和向后移位操作。
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