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    THIN FILM TRANSISTOR AND ELECTRONIC DEVICE
    2.
    发明申请
    THIN FILM TRANSISTOR AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20250081540A1

    公开(公告)日：2025-03-06

    申请号：US18950230

    申请日：2024-11-18

    Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

    IPC: H01L29/786 ,  H01L29/04 ,  H01L29/06 ,  H01L29/49

    Abstract: A thin film transistor includes an oxide semiconductor layer having a polycrystalline structure over a substrate, a gate electrode over the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a first region having a first carrier concentration and overlapping the gate electrode, a second region having a second carrier concentration and not overlapping the gate electrode, and a third region between the first region and the second region and overlapping the gate electrode. The second carrier concentration is larger than the first carrier concentration. A carrier concentration of the third region decreases from the second region to the first region in a channel length direction. A length of the third region is greater than or equal to 0.00 μm and less than or equal to 0.60 μm in the channel length direction.

    THIN FILM TRANSISTOR AND ELECTRONIC DEVICE
    3.
    发明申请
    THIN FILM TRANSISTOR AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20250015196A1

    公开(公告)日：2025-01-09

    申请号：US18889394

    申请日：2024-09-19

    Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

    IPC: H01L29/786 ,  H01L29/66

    Abstract: A thin film transistor includes a metal oxide layer over the substrate, an oxide semiconductor layer having crystallinity in contact with the metal oxide layer, a gate electrode overlapping the oxide semiconductor layer, and an insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation , a crystal orientation , and a crystal orientation obtained by an EBSD method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation is less than or equal to 5%.

    THIN FILM TRANSISTOR AND ELECTRONIC DEVICE
    4.
    发明申请
    THIN FILM TRANSISTOR AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20250006783A1

    公开(公告)日：2025-01-02

    申请号：US18830651

    申请日：2024-09-11

    Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

    IPC: H01L29/04 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

    Abstract: A thin film transistor includes an oxide semiconductor layer having crystallinity over a substrate, a gate electrode overlapping the oxide semiconductor layer, and an insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation , a crystal orientation , and a crystal orientation obtained by an EBSD method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation is greater than an occupancy rate of the crystal orientation and an occupancy rate of the crystal orientation .

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240379865A1

    公开(公告)日：2024-11-14

    申请号：US18651909

    申请日：2024-05-01

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

    IPC: H01L29/786 ,  H01L29/417

    Abstract: A semiconductor device according to an embodiment of the present invention includes: a gate electrode; a gate insulating layer; a metal oxide layer containing aluminum as a main component above the gate insulating layer; an oxide semiconductor layer having a polycrystalline structure above the metal oxide layer; a source electrode and a drain electrode contacting the oxide semiconductor layer from above the oxide semiconductor layer; and an insulating layer above the source electrode and the drain electrode, wherein a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg−Vth)×Cox=5×10−7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer.

    SEMICONDUCTOR DEVICE
    8.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240312999A1

    公开(公告)日：2024-09-19

    申请号：US18588249

    申请日：2024-02-27

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

    IPC: H01L27/12

    CPC classification number: H01L27/1225 ,  H01L27/1251

    Abstract: A semiconductor device includes a first transistor on a substrate and a second transistor on the first transistor. The first transistor includes a first gate electrode on the substrate, a first insulating film on the first gate electrode, a first oxide semiconductor layer on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure, a second insulating film on the first oxide semiconductor layer, and a second gate electrode on the second insulating film. The second transistor includes a third gate electrode on the second insulating film, a third insulating film on the third gate electrode, a second oxide semiconductor layer on the third insulating film and having a region overlapping the third gate electrode, a fourth insulating film on the second oxide semiconductor layer, and a fourth gate electrode on the fourth insulating film.

    SEMICONDUCTOR DEVICE
    9.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240178325A1

    公开(公告)日：2024-05-30

    申请号：US18519392

    申请日：2023-11-27

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

    IPC: H01L29/786 ,  H01L29/06

    CPC classification number: H01L29/7869 ,  H01L29/0603 ,  H01L29/78696

    Abstract: A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping the gate electrode, and source and drain regions that do not overlap the gate electrode. At an interface between the source and drain regions and the gate insulating layer, a concentration of an impurity on a surface of at least one of the source and drain regions is greater than or equal to 1×1019 cm−3.

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    10.
    发明公开
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240105819A1

    公开(公告)日：2024-03-28

    申请号：US18474389

    申请日：2023-09-26

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

    CPC classification number: H01L29/66969 ,  H01L21/02667 ,  H01L29/7869

    Abstract: A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.

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