公开(公告)号：US08583851B2

公开(公告)日：2013-11-12

申请号：US13776231

申请日：2013-02-25

Applicant: Juniper Networks, Inc.

Inventor： Anjan Venkatramani ,  Srinivas Perla ,  John Keen

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F12/0607 ,  G06F12/0615 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1652

Abstract: A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank.

Abstract translation: 设备可以接收从包括多个存储体的存储器读取数据或向数据写入数据的请求。 请求可能包含一个地址。 设备可以对地址执行映射操作，以将地址从第一地址空间映射到第二地址空间，基于第二地址空间中的地址识别存储体之一，并将该请求发送到所识别的存储体 。

公开(公告)号：US09098262B2

公开(公告)日：2015-08-04

申请号：US14529331

申请日：2014-10-31

Applicant: Juniper Networks, Inc.

Inventor： Jean-Marc Frailong ,  Pradeep S. Sindhu ,  Jeffrey G. Libby ,  Jian Hui Huang ,  Rajesh Nair ,  John Keen

IPC: G06F9/28 ,  G06F15/00 ,  G06F9/30

CPC classification number: G06F9/28 ,  G06F7/57 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3859 ,  G06F9/3893 ,  G06F15/00

Abstract: A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.

Abstract translation: 处理器可以包括条件算术逻辑单元和主算术逻辑单元。 条件算术逻辑单元可以执行第一算术逻辑运算以产生第一结果，并输出结果。 主算术逻辑单元可以选择携带来自条件算术逻辑单元的第一结果的多个数据总线中的输入总线，对由所选择的输入总线提供的数据执行第二运算逻辑运算以产生第二结果，并写入 第二个结果是存储组件。

公开(公告)号：US09391958B2

公开(公告)日：2016-07-12

申请号：US14318830

申请日：2014-06-30

Applicant: JUNIPER NETWORKS, INC.

Inventor： Venkatasubramanian Swaminathan ,  Deepak Goel ,  Jianhui Huang ,  John Keen ,  Jean-Marc Frailong ,  Srinivasan Jagannadhan ,  Srilakshmi Adusumalli

IPC: H04L29/06

CPC classification number: H04L63/0263 ,  H04L63/02 ,  H04L63/0209

Abstract: A firewall device may include a forwarding component that includes a filter block. The filter block may obtain a first hardware-implemented filter, where a hardware implementation limits the first hardware-implemented filter to a maximum quantity of rules; determine whether a last rule associated with the accessed hardware-implemented filter includes a split-filter action, where the split-filter action identifies a second hardware-implemented filter; and link the second hardware-implemented filter to the first hardware-implemented filter to make the second hardware-implemented filter a logical continuation of the first hardware-implemented filter, in response to determining that the last rule includes the split-filter action. The filter block may further determine whether a particular rule of the first hardware-implemented filter includes a next-filter action, where the next filter action identifies a third hardware-implemented filter; and process the third hardware-implemented filter independently of the sequence of hardware attachment points.

Abstract translation: 防火墙设备可以包括包括过滤器块的转发组件。 滤波器块可以获得第一硬件实现的滤波器，其中硬件实现将第一硬件实现的滤波器限制为最大数量的规则; 确定与所访问的硬件实现的过滤器相关联的最后规则是否包括拆分过滤器动作，其中分割过滤器动作标识第二硬件实现的过滤器; 以及响应于确定所述最后一个规则包括所述分割过滤器动作，将所述第二硬件实现的过滤器链接到所述第一硬件实现的过滤器，以使得所述第二硬件实现的过滤器是所述第一硬件实现的过滤器的逻辑延续。 滤波器块还可以确定第一硬件实现的滤波器的特定规则是否包括下一个滤波器动作，其中下一个滤波器动作识别第三硬件实现的滤波器; 并且独立于硬件连接点的顺序处理第三个硬件实现的过滤器。