Methods and apparatus for a scheduler for memory access

    公开(公告)号:US10157123B1

    公开(公告)日:2018-12-18

    申请号:US15799013

    申请日:2017-10-31

    Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.

    Methods and apparatus for a scheduler for memory access

    公开(公告)号:US09811453B1

    公开(公告)日:2017-11-07

    申请号:US13955733

    申请日:2013-07-31

    Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.

    Partitioning a filter to facilitate filtration of packets

    公开(公告)号:US10097516B2

    公开(公告)日:2018-10-09

    申请号:US15457417

    申请日:2017-03-13

    Abstract: A method may include obtaining a match vector that indicates one or more filter rules that are potentially applicable to a packet. The method may include partitioning the match vector into a plurality of segments. The method may include generating a summary vector that identifies one or more portions of the match vector that include one or more match bits. A match bit may indicate one of the one or more filter rules that is potentially applicable to the packet. The method may include obtaining a relevant segment of the match vector. The relevant segment may include at least one of the portions of the match vector identified by the summary vector. The method may include determining a filter rule to apply based on the match vector and based on the one or more match bits. The method may include applying the filter rule to the packet.

    PARTITIONING A FILTER TO FACILITATE FILTRATION OF PACKETS

    公开(公告)号:US20170187687A1

    公开(公告)日:2017-06-29

    申请号:US15457417

    申请日:2017-03-13

    Abstract: A method may include obtaining a match vector that indicates one or more filter rules that are potentially applicable to a packet. The method may include partitioning the match vector into a plurality of segments. The method may include generating a summary vector that identifies one or more portions of the match vector that include one or more match bits. A match bit may indicate one of the one or more filter rules that is potentially applicable to the packet. The method may include obtaining a relevant segment of the match vector. The relevant segment may include at least one of the portions of the match vector identified by the summary vector. The method may include determining a filter rule to apply based on the match vector and based on the one or more match bits. The method may include applying the filter rule to the packet.

    Partitioning a filter to facilitate filtration of packets
    5.
    发明授权
    Partitioning a filter to facilitate filtration of packets 有权
    分隔一个过滤器以方便过滤数据包

    公开(公告)号:US09596215B1

    公开(公告)日:2017-03-14

    申请号:US14696702

    申请日:2015-04-27

    Abstract: A method may include obtaining a match vector that indicates one or more filter rules that are potentially applicable to a packet. The method may include partitioning the match vector into a plurality of segments. The method may include generating a summary vector that identifies one or more portions of the match vector that include one or more match bits. A match bit may indicate one of the one or more filter rules that is potentially applicable to the packet. The method may include obtaining a relevant segment of the match vector. The relevant segment may include at least one of the portions of the match vector identified by the summary vector. The method may include determining a filter rule to apply based on the match vector and based on the one or more match bits. The method may include applying the filter rule to the packet.

    Abstract translation: 方法可以包括获得指示可能适用于分组的一个或多个过滤规则的匹配向量。 该方法可以包括将匹配向量划分成多个段。 该方法可以包括生成识别包括一个或多个匹配位的匹配向量的一个或多个部分的汇总向量。 匹配位可以指示可能适用于分组的一个或多个过滤规则之一。 该方法可以包括获得匹配向量的相关段。 相关段可以包括由汇总向量识别的匹配向量的至少一个部分。 该方法可以包括基于匹配向量并且基于一个或多个匹配比特来确定要应用的滤波器规则。 该方法可以包括将过滤规则应用于分组。

    Hardware implementation of complex firewalls using chaining technique
    6.
    发明授权
    Hardware implementation of complex firewalls using chaining technique 有权
    使用链接技术的复杂防火墙的硬件实现

    公开(公告)号:US09391958B2

    公开(公告)日:2016-07-12

    申请号:US14318830

    申请日:2014-06-30

    CPC classification number: H04L63/0263 H04L63/02 H04L63/0209

    Abstract: A firewall device may include a forwarding component that includes a filter block. The filter block may obtain a first hardware-implemented filter, where a hardware implementation limits the first hardware-implemented filter to a maximum quantity of rules; determine whether a last rule associated with the accessed hardware-implemented filter includes a split-filter action, where the split-filter action identifies a second hardware-implemented filter; and link the second hardware-implemented filter to the first hardware-implemented filter to make the second hardware-implemented filter a logical continuation of the first hardware-implemented filter, in response to determining that the last rule includes the split-filter action. The filter block may further determine whether a particular rule of the first hardware-implemented filter includes a next-filter action, where the next filter action identifies a third hardware-implemented filter; and process the third hardware-implemented filter independently of the sequence of hardware attachment points.

    Abstract translation: 防火墙设备可以包括包括过滤器块的转发组件。 滤波器块可以获得第一硬件实现的滤波器,其中硬件实现将第一硬件实现的滤波器限制为最大数量的规则; 确定与所访问的硬件实现的过滤器相关联的最后规则是否包括拆分过滤器动作,其中分割过滤器动作标识第二硬件实现的过滤器; 以及响应于确定所述最后一个规则包括所述分割过滤器动作,将所述第二硬件实现的过滤器链接到所述第一硬件实现的过滤器,以使得所述第二硬件实现的过滤器是所述第一硬件实现的过滤器的逻辑延续。 滤波器块还可以确定第一硬件实现的滤波器的特定规则是否包括下一个滤波器动作,其中下一个滤波器动作识别第三硬件实现的滤波器; 并且独立于硬件连接点的顺序处理第三个硬件实现的过滤器。

    TWO STAGE BLOOM FILTER FOR LONGEST PREFIX MATCH

    公开(公告)号:US20170187624A1

    公开(公告)日:2017-06-29

    申请号:US15454658

    申请日:2017-03-09

    Abstract: A device may receive a packet that includes a destination address. The device may analyze a first Bloom filter, based on the destination address, in order to identify a prefix range entry associated with the destination address and included in a set of prefix range entries associated with the first Bloom filter. The device may analyze a second Bloom filter, based on the destination address and the identified prefix range entry, in order to identify a prefix length entry associated with the destination address and included in a set of prefix length entries associated with the second Bloom filter. The device may determine routing information associated with the identified prefix length entry. The routing information may identify a longest prefix match associated with the destination address. The device may provide the packet based on the routing information.

    Methods and apparatus to implement except condition during data packet classification
    8.
    发明授权
    Methods and apparatus to implement except condition during data packet classification 有权
    在数据包分类期间实现除条件之外的方法和装置

    公开(公告)号:US09413660B1

    公开(公告)日:2016-08-09

    申请号:US14312283

    申请日:2014-06-23

    CPC classification number: H04L45/745 H04L45/302

    Abstract: In one embodiment, a method includes receiving a value associated with a data packet and identifying a data set based on the value. The data set is associated with a range of values and represents routing actions. The data set is a first data set from a plurality of data sets if the value is included in the range of values associated with the first data set. The data set is a default data set if the value is not included in a range of values associated with a data set from the plurality of data sets. The method includes combining the first data set with the default data set if the first data set is identified. The method includes combining the default data set with an except data set if the default data set is identified.

    Abstract translation: 在一个实施例中,一种方法包括接收与数据分组相关联的值并基于该值识别数据集。 数据集与值的范围相关联,并表示路由动作。 如果该值包括在与第一数据集相关联的值的范围内,则数据集是来自多个数据集的第一数据集。 如果该值不包括在与多个数据集中的数据集相关联的值的范围内,则数据集是默认数据集。 该方法包括如果识别出第一数据集,则将第一数据集合与默认数据集合。 该方法包括如果识别出默认数据集,则将默认数据集与除数据集合组合。

    Scalable switch fabric cell reordering

    公开(公告)号:US10164906B1

    公开(公告)日:2018-12-25

    申请号:US14871669

    申请日:2015-09-30

    Abstract: In some examples, a switching system includes a plurality of fabric endpoints and a multi-stage switching fabric. A fabric endpoint of the system is configured to receive, via the switch fabric, a plurality of cell streams, wherein each cell of a cell stream of the plurality of cell stream is associated with a sequence number that defines a correct ordering of cells of the cell stream; assign subsequences of each cell stream of the plurality of cell streams to respective reorder engines of the fabric endpoint; concurrently reorder the assigned respective subsequences to produce respective ordered subsequences for the subsequences, wherein the ordered subsequences are ordered according to the correct ordering of the corresponding cell stream; interleave the respective ordered subsequences for each cell stream to produce reordered cell streams each having correctly ordered cells; and process each reordered cell stream according to the corresponding correct ordering of cells.

    Two stage bloom filter for longest prefix match

    公开(公告)号:US10158571B2

    公开(公告)日:2018-12-18

    申请号:US15454658

    申请日:2017-03-09

    Abstract: A device may receive a packet that includes a destination address. The device may analyze a first Bloom filter, based on the destination address, in order to identify a prefix range entry associated with the destination address and included in a set of prefix range entries associated with the first Bloom filter. The device may analyze a second Bloom filter, based on the destination address and the identified prefix range entry, in order to identify a prefix length entry associated with the destination address and included in a set of prefix length entries associated with the second Bloom filter. The device may determine routing information associated with the identified prefix length entry. The routing information may identify a longest prefix match associated with the destination address. The device may provide the packet based on the routing information.

Patent Agency Ranking