公开(公告)号：US07764209B2

公开(公告)日：2010-07-27

申请号：US12209795

申请日：2008-09-12

申请人： Isao Tottori ,  Masaru Hagiwara

发明人： Isao Tottori ,  Masaru Hagiwara

IPC分类号： H03M1/00

CPC分类号： G06F13/423

摘要： A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

摘要翻译： CPU响应来自缓冲器的请求，将数字数据从内置RAM输出到缓冲器。 缓冲器具有由多个级构成的FIFO，FIFO的每一级能够存储数字数据的一个单元（10位），因此整个缓冲器能够存储与数字等价的单元数量的数字数据 的配置阶段。 寄存器与输出控制时钟同步，通过每个单元捕获存储在缓冲器内的数字数据。 存储在寄存器中的数字数据作为D / A转换的数据输出到并行DAC。 WR信号输出定时器产生与输出控制时钟同步的具有“L”的单次脉冲的写入控制信号。

公开(公告)号：US07978108B2

公开(公告)日：2011-07-12

申请号：US12762955

申请日：2010-04-19

申请人： Isao Tottori ,  Masaru Hagiwara

发明人： Isao Tottori ,  Masaru Hagiwara

IPC分类号： H03M1/00

CPC分类号： G06F13/423

摘要： A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

摘要翻译： CPU响应来自缓冲器的请求，将数字数据从内置RAM输出到缓冲器。 缓冲器具有由多个级组成的FIFO，FIFO的每一级能够存储数字数据的一个单元（10位），因此整个缓冲器能够存储与数字等价的单元数量的数字数据 的配置阶段。 寄存器与输出控制时钟同步，通过每个单元捕获存储在缓冲器内的数字数据。 存储在寄存器中的数字数据作为D / A转换的数据输出到并行DAC。 WR信号输出定时器产生与输出控制时钟同步的具有“L”的单次脉冲的写入控制信号。

公开(公告)号：US06368956B2

公开(公告)日：2002-04-09

申请号：US09780461

申请日：2001-02-12

申请人： Isao Tottori

发明人： Isao Tottori

IPC分类号： H01L214763

CPC分类号： H01L21/76819 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834

摘要： On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.

摘要翻译： 在覆盖栅电极部分的氧化硅膜上形成回流抛光的BPSG膜。 在BPSG膜上形成第二互连层。 为了覆盖第二互连层，在氧化硅膜上形成厚度至少为第二互连层的实质厚度的氧化硅膜。 因此，能够确保互连层的基底的平坦性，并抑制互连层的位移。 因此，获得了具有高集成度的半导体器件。

公开(公告)号：US5479054A

公开(公告)日：1995-12-26

申请号：US019252

申请日：1993-02-18

申请人： Isao Tottori

发明人： Isao Tottori

IPC分类号： H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321 ,  H01L23/485

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2924/0002

摘要： A polycrystalline silicon film is formed on the surface of a semiconductor substrate. An oxide film having a first impurity concentration is formed to cover the polycrystalline silicon film. A polycrystalline silicon film and a refractory metal silicide are formed on the surface of the oxide film having the first impurity concentration. An oxide film having a second impurity concentration higher than the first impurity concentration is formed to cover the polycrystalline silicon film and the refractory metal silicide. The third conductive layer is formed on the surface of the oxide film having the second impurity concentration.

摘要翻译： 在半导体衬底的表面上形成多晶硅膜。 形成具有第一杂质浓度的氧化膜以覆盖多晶硅膜。 在具有第一杂质浓度的氧化物膜的表面上形成多晶硅膜和难熔金属硅化物。 形成具有高于第一杂质浓度的第二杂质浓度的氧化物膜以覆盖多晶硅膜和难熔金属硅化物。 第三导电层形成在具有第二杂质浓度的氧化物膜的表面上。

公开(公告)号：US5047127A

公开(公告)日：1991-09-10

申请号：US560878

申请日：1990-07-31

申请人： Isao Tottori ,  Masazumi Matsuura ,  Atsuhiro Fujii

发明人： Isao Tottori ,  Masazumi Matsuura ,  Atsuhiro Fujii

IPC分类号： C01B13/11

CPC分类号： C01B13/11 ,  C01B2201/60 ,  C01B2201/76 ,  C01B2201/80

摘要： An ozone generating method for increasing the quantity of ozone produced by a silent discharge in high purity oxygen includes mixing nitrogen with the high purity oxygen in a predetermined ratio. The nitrogen gas is a catalyst for stable and highly efficient ozone generation from a high purity oxygen source.

摘要翻译： 用于增加在高纯度氧气中通过无声放电产生的臭氧量的臭氧发生方法包括以预定比例将氮气与高纯度氧气混合。 氮气是用于从高纯度氧源产生稳定且高效的臭氧的催化剂。

公开(公告)号：US06265778B1

公开(公告)日：2001-07-24

申请号：US09496953

申请日：2000-02-03

申请人： Isao Tottori

发明人： Isao Tottori

IPC分类号： H01L2358

CPC分类号： H01L23/5283 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with a multi-level interconnection structure has a first conductive layer disposed below a fuse, and formed in the same layer as the first metal wire as a component of multi-level interconnects, and a second conductive layer disposed below the fuse and formed in the same layer as the second metal wire as a component of the multi-level interconnects. A laser beam control unit is configured with the first and second conductive layers. Thus, damage occurrence in a semiconductor substrate may be controlled during blowing the fuse, a quality deterioration and further a defective of the semiconductor device may be not only avoided, but also an integration degree thereof may be enhanced.

摘要翻译： 具有多电平互连结构的半导体器件具有设置在熔丝下方的第一导电层，并且形成在与第一金属线作为多电平互连部件的同一层中，以及设置在熔丝下方的第二导电层， 形成在与作为多层互连的部件的第二金属线相同的层中。 激光束控制单元配置有第一和第二导电层。 因此，可以在熔断器熔断期间控制半导体衬底中的损坏，不仅可以避免质量劣化，还可以避免半导体器件的缺陷，而且可以提高其集成度。

公开(公告)号：US5930674A

公开(公告)日：1999-07-27

申请号：US518019

申请日：1995-08-22

申请人： Isao Tottori

发明人： Isao Tottori

IPC分类号： H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/473

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2924/0002

摘要： A polycrystalline silicon film is formed on the surface of a semiconductor substrate. An oxide film having a first impurity concentration is formed to cover the polycrystalline silicon film. A polycrystalline silicon film and a refractory metal silicide are formed on the surface of the oxide film having the first impurity concentration. An oxide film having a second impurity concentration higher than the first impurity concentration is formed to cover the polycrystalline silicon film and the refractory metal silicide. The third conductive layer is formed on the surface of the oxide film having the second impurity concentration.

公开(公告)号：US06207987B1

公开(公告)日：2001-03-27

申请号：US09198363

申请日：1998-11-24

申请人： Isao Tottori

发明人： Isao Tottori

IPC分类号： H07L27108

CPC分类号： H01L21/76819 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834

摘要： On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.

摘要翻译： 在覆盖栅电极部分的氧化硅膜上形成回流抛光的BPSG膜。 在BPSG膜上形成第二互连层。 为了覆盖第二互连层，在氧化硅膜上形成厚度至少为第二互连层的实质厚度的氧化硅膜。 因此，能够确保互连层的基底的平坦性，并抑制互连层的位移。 因此，获得了具有高集成度的半导体器件。

公开(公告)号：US5460691A

公开(公告)日：1995-10-24

申请号：US227710

申请日：1994-04-14

申请人： Kiyoteru Kobayashi ,  Isao Tottori

发明人： Kiyoteru Kobayashi ,  Isao Tottori

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  B44C1/22

CPC分类号： H01J37/32449 ,  H01L21/31116 ,  Y10S438/935

摘要： It is an object of the present invention to provide a method capable of performing surface treatment of a plurality of semiconductor substrates at one time and treating them uniformly with high selectivity. A plurality of semiconductor substrates having interlayer insulating films thereon are prepared. The plurality of semiconductor substrates are arranged in a vertical direction at predetermined intervals in a reaction chamber so that one face of each faces upwards and the other face of each faces downwards. Etching gas for etching the surfaces of the interlayer insulating films is sent into the reaction chamber in a direction vertical to the surfaces of said semiconductor substrates under low pressure.

摘要翻译： 本发明的目的是提供能够一次进行多个半导体基板的表面处理并以高选择性均匀地进行处理的方法。 制备其上具有层间绝缘膜的多个半导体衬底。 多个半导体基板在反应室中以预定间隔沿垂直方向布置，使得每个半导体基板的一个面朝上，另一个面朝下。 用于蚀刻层间绝缘膜的表面的蚀刻气体在低压下沿垂直于所述半导体衬底的表面的方向被送入反应室。